User’s Manual

IBM PowerPC 750GX and 750GL RISC Microprocessor

L2 interface

cache global invalidation, 329 cache initialization, 329 cache testing, 333

dcbi, 328 eieio, 328 operation, 323 stwcx. execution, 328 sync, 328

load/store operations, processor initiated, 130 miss, 222

operations

cache block push operations, 328 data cache transactions, 140 instruction cache block fill, 139

snoop response to bus transactions, 143 PLRU replacement, 137

stwcx. execution, 328

Changed (C) bit maintenance recording, 188, 198 Checkstop

signal, 169, 271 state, 169

CI (cache inhibit) signal, 260

CKSTP_IN/CKSTP_OUT(checkstop input/output) signals , 169, 271

Classes of instructions, 87 Clean block operation, 143 Clock signals

PLL_CFGn, 277

SYSCLK, 277 Completion

completion unit resource requirements, 237 considerations, 224

definition, 209 Context synchronization, 90 Conventions, 209 COP/scan interface, 319 Copy-back mode, 235

CR (condition register)

CR logical instructions, 107 CR, description, 59

CTR register, 59

D

DABR (data address breakpoint register), 62 DAR (data address register), 61

Data bus

arbitration signals, 264, 285 bus arbitration, 301

data tenure, 285

data transfer, 266, 303

data transfer termination, 268, 303 Data cache

configuration, 123

DCFI, DCE, DLOCK bits, 132 organization, 123

Data organization in memory, 82 Data transfers

alignment, 296 burst ordering, 295

eciwx and ecowx instructions, alignment, 300 operand conventions, 82

signals, 303

DBB (data bus busy) signal, 286, 302 DBG (data bus grant) signal, 264, 285

DBWO (data bus write only) signal, 286, 303, 320 DEC (decrementer register), 62

Decrementer exception, 171 Defined instruction class, 87 DHn/DLn (data bus) signals, 266 Dispatch

considerations, 224

dispatch unit resource requirements, 237 DRTRY (data retry) signal, 269, 303, 306 DSI exception, 169

DSISR register, 61 DTLB organization, 200 Dynamic branch prediction, 216

E

EAR (external access register), 62 Effective address calculation

address translation, 181 branches, 90

loads and stores, 90, 99, 103

eieio, enforce in-order execution of I/O, 115 EMI protocol, enforcing memory coherency, 308 Error termination, 307

Event counting, 355 Event selection, 356 Exceptions

alignment exception, 170 decrementer exception, 171 definitions, 162

DSI exception, 169

enabling and disabling exceptions, 160 exception classes, 152

exception prefix (IP) bit, 163 exception priorities, 153 exception processing, 156, 160 external interrupt, 169

FP assist exception, 171

FP unavailable exception, 171 instruction-related exceptions, 91 ISI exception, 169

machine check exception, 167 performance monitor interrupt, 172 program exception, 170

Index

750gx_umIX.fm.(1.2)

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March 27, 2006