IBM 750GL, 750GX 9.3 L2 Cache Control Register (L2CR), 9.4 L2 Cache Initialization, 9.5 L2 Cache Global Invalidation

User’s Manual

IBM PowerPC 750GX and 750GL RISC Microprocessor

9.3 L2 Cache Control Register (L2CR)

The L2 Cache Control Register is used to configure and enable the L2 cache. The L2CR is a supervisor-level read/write, implementation-specific register that is accessed as Special Purpose Register (SPR) 1017. The contents of the L2CR are cleared during power-on reset. For a full description of L2CR and its bits, see Section 2.1.5, L2 Cache Control Register (L2CR), on page 81.

9.4 L2 Cache Initialization

The L2 cache is initially disabled following a power-on or hard reset. Before enabling the L2 cache, other configuration parameters must be set in the L2CR, and the L2 tags must be globally invalidated. The L2 cache should be initialized during system start-up.

The sequence for initializing the L2 cache is as follows.

1.Power-on reset (automatically performed by the assertion of the HRESET signal).

2.Disable interrupts and dynamic power management (DPM).

3.Disable L2 cache by clearing L2CR[L2E].

4.Perform an L2 global invalidate as described in Section 9.5.

5.After the L2 global invalidate has been performed, and the other L2 configuration bits have been set, enable the L2 cache for normal operation by setting the L2CR[L2E] bit to 1.

9.5 L2 Cache Global Invalidation

The L2 cache supports a global invalidation function in which all bits of the L2 tags (tag data bits, tag status bits, and LRU bit) are cleared. It is performed by an on-chip hardware state machine that sequentially cycles through the L2 tags. The global invalidation function is controlled through L2CR[GI], and it must be performed only while the L2 cache is disabled.

The sequence for performing a global invalidation of the L2 cache is as follows:

1.Flush the L2 to save any modified data.

2.Execute a sync instruction to finish any pending store operations in the load/store unit, disable the L2 cache by clearing L2CR[L2E], and execute an additional sync instruction after disabling the L2 cache to ensure that any pending operations in the L2 cache unit have completed.

3.Initiate the global invalidation operation by setting the L2CR[GI] bit to 1.

4.Monitor the L2CR[IP] bit to determine when the global invalidation operation is complete (indicated by the clearing of L2CR[IP]). The global invalidation requires approximately 32 K core clock cycles to complete.

5.After detecting the clearing of L2CR[IP], clear L2CR[GI] and re-enable the L2 cache for normal operation by setting L2CR[L2E].

Never perform a global invalidation of the L2 cache while in dynamic power-management enable mode. Be sure the HID0[DPM] bit is zero. Also ensure that the processor is in a tight, uninterruptable software loop monitoring the end of the global invalidate, so that an L1 data-cache miss cannot occur that would initiate a reload from system memory during the global invalidate operation.

gx_09.fm.(1.2)	L2 Cache
March 27, 2006	Page 329 of 377