User’s Manual

IBM PowerPC 750GX and GL RISC Microprocessor

System reset and machine-check exceptions can occur at any time and are not delayed even if an exception is being handled. As a result, state information for an interrupted exception might be lost. Therefore, these exceptions are typically nonrecoverable. An exception might not be taken immediately when it is recognized.

4.3 Exception Processing

When an exception is taken, the processor uses Machine Status Save/Restore Register 0 (SRR0) to determine where instruction processing should resume, and uses Machine Status Save/Restore Register 1 (SRR1) to save the contents of the Machine State Register (MSR) for the current context.

4.3.1 Machine Status Save/Restore Register 0 (SRR0)

When an exception occurs, the address saved in SRR0 determines where instruction processing should resume when the exception handler returns control to the interrupted process. Depending on the exception, this might be the address in SRR0 or the next address in the program flow. All instructions in the program flow preceding this one will have completed execution, and no subsequent instruction will have begun execution. This might be the address of the instruction that caused the exception or the next one (as in the case of a system call, trace, or trap exception).

SRR0

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Exceptions

gx_04.fm.(1.2)

Page 156 of 377

March 27, 2006