IBM 750GL, 750GX 2.3.6.3 Memory Control Instructions—OEA

User’s Manual

IBM PowerPC 750GX and 750GL RISC Microprocessor

2.3.6.3 Memory Control Instructions—OEA

Memory control instructions include the following.

•Cache-management instructions (supervisor-level and user-level).

•Segment register manipulation instructions.

•Translation-lookaside-buffer management instructions.

This section describes supervisor-level memory control instructions. Section 2.3.5.3, Memory Control Instruc- tions—VEA,on page 115 describes user-level memory control instructions.

Supervisor-Level Cache-Management Instruction—(OEA)

Table 2-43lists the only supervisor-level cache-management instruction.

Table 2-43. Supervisor-Level Cache-Management Instruction

Name	Mnemonic	Syntax		Implementation Notes
			The EA is computed, translated, and checked for protection violations. For cache hits, the
			cache block is marked invalid (I) regardless of whether it was marked exclusive unmodified
			(E) or exclusive modified (M). A dcbi is not broadcast unless HID0[ABE] = 1, regardless of
Data Cache Block	dcbi	rA,rB	WIMG settings. The instruction acts like a store with respect to address translation and
			memory protection. It executes regardless of whether the cache is disabled or locked.
Invalidate
			The exception priorities (from highest to lowest) for dcbi are as follows:
			1	BAT protection violation—DSI exception.
			2	TLB protection violation—DSI exception.

See User-Level Cache Instructions—VEAon page 115 for cache instructions that provide user-level programs the ability to manage the on-chip caches. If the effective address references a direct-store segment, then the instruction is treated as a no-op.

Segment Register Manipulation Instructions (OEA)

The instructions listed in Table 2-44provide access to the Segment Registers for 32-bit implementations. These instructions operate completely independently of the MSR[IR] and MSR[DR] bit settings. See “Synchronization Requirements for Special Registers and for Lookaside Buffers” in Chapter 2, “PowerPC Register Set” of the PowerPC Microprocessor Family: The Programming Environments Manual for serialization requirements and other recommended precautions to observe when manipulating the Segment Regis- ters. Be sure to execute an isync after execution of an mtsr instruction.

Table 2-44. Segment Register Manipulation Instructions

Name	Mnemonic	Syntax	Implementation Notes
Move-to Segment Register	mtsr	SR,rS	Execute isync after mtsr.
Move-to Segment Register Indirect	mtsrin	rS,rB	Execute isync after mtsrin.
Move-from Segment Register	mfsr	rD,SR	The shadow SRs in the instruction MMU can be read by setting
			HID0[RISEG] before executing mfsr.
Move-from Segment Register Indirect	mfsrin	rD,rB	—

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