User’s Manual

IBM PowerPC 750GX and 750GL RISC Microprocessor

Note: The PowerPC Architecture states that, in some implementations, the move-to FPSCR fields (mtfsf) instruction might perform more slowly when only some of the fields are updated as opposed to all of the fields. In the 750GX, there is no degradation of performance.

Floating-Point Move Instructions

Floating-point move instructions copy data from one FPR to another. The floating-point move instructions do not modify the FPSCR. The CR update option in these instructions controls the placing of result status into CR1. Table 2-17summarizes the floating-point move instructions.

Table 2-17. Floating-Point Move Instructions

Name

Mnemonic

Syntax

 

 

 

 

 

 

 

 

Floating Move Register

fmr

(fmr.)

frD,frB

 

 

 

 

Floating Negate

fneg

(fneg.)

frD,frB

 

 

 

 

Floating Absolute Value

fabs

(fabs.)

frD,frB

 

 

 

 

Floating Negative Absolute Value

fnabs

(fnabs.)

frD,frB

 

 

 

 

2.3.4.3 Load-and-Store Instructions

Load-and-store instructions are issued and translated in program order; however, the accesses can occur out of order. Synchronizing instructions are provided to enforce strict ordering. This section describes the load- and-store instructions, which consist of the following:

•Integer load instructions

•Integer store instructions

•Integer load-and-store with byte-reverse instructions

•Integer load-and-store multiple instructions

•Floating-point load instructions, including quantized loads

•Floating-point store instructions, including quantized stores

•Memory synchronization instructions

The 750GX provides hardware support for misaligned memory accesses. It performs those accesses within a single cycle if the operand lies within a double-word boundary. Misaligned memory accesses that cross a double-word boundary degrade performance.

For string operations, the hardware makes no attempt to combine register values to reduce the number of discrete accesses. Combining stores enhances performance if store gathering is enabled and the accesses meet the criteria described in Section 6.4.7, Integer Store Gathering, on page 234. Note that the PowerPC Architecture requires load/store multiple instruction accesses to be aligned. At a minimum, additional cache access cycles are required.

Although many unaligned memory accesses are supported in hardware, the frequent use of them is discouraged since they can compromise the overall performance of the processor.

Accesses that cross a translation boundary might be restarted. That is, a misaligned access that crosses a page boundary is completely restarted if the second portion of the access causes a page fault. This might cause the first access to be repeated. On some processors, such as the PowerPC 603, a TLB reload would cause an instruction restart. On the 750GX, TLB reloads are done transparently, and only a page fault causes a restart.

Programming Model

gx_02.fm.(1.2)

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March 27, 2006