User’s Manual

IBM PowerPC 750GX and 750GL RISC Microprocessor

8.7 Processor State Signals

This section describes the 750GX's support for atomic update and memory through the use of the lwarx and

stwcx. opcode pair, and includes a description of the TLB Invalidate Synchronize (TLBISYNC) input.

8.7.1 Support for the lwarx and stwcx. Instruction Pair

The Load Word and Reserve Indexed (lwarx) and the Store Word Conditional Indexed (stwcx.) instructions provide a means for atomic memory updating. Memory can be updated atomically by setting a reservation on the load and checking that the reservation is still valid before the store is performed. In the 750GX, the reservations are made on behalf of aligned, 32-byte sections of the memory address space.

The reservation (RSRV) output signal is driven synchronously with the bus clock and reflects the status of the reservation coherency bit in the Reservation Address Register; see Chapter 3, Instruction-Cache and Data- Cache Operation, on page 121 for more information. For information about timing, see Section 7.2.11.3, Reservation (RSRV)—Output,on page 273.

8.7.2 TLBISYNC Input

The TLBISYNC input allows for the hardware synchronization of changes to MMU tables when the 750GX and another direct memory access (DMA) master share the same MMU translation tables in system memory. It is asserted by a DMA master when it is using shared addresses that could be changed in the MMU tables by the 750GX during the DMA master’s tenure.

The TLBISYNC input, when asserted to the 750GX, prevents the 750GX from completing any instructions past a TLB Synchronize (tlbsync) instruction. Generally, during the execution of an eciwx or ecowx instruction by the 750GX, the selected DMA device should assert the 750GX’s TLBISYNC signal and maintain it asserted during its DMA tenure if it is using a shared translation address. Subsequent instructions by the 750GX should include a sync and tlbsync instruction before any MMU table changes are performed. This will prevent the 750GX from making table changes disruptive to the other master during the DMA period.

8.8 IEEE 1149.1a-1993 Compliant Interface

The 750GX boundary-scan interface is a fully-compliant implementation of the IEEE 1149.1a-1993 standard. This section describes the 750GX’s IEEE 1149.1a-1993 (JTAG) interface.

8.8.1 JTAG/COP Interface

The 750GX has extensive on-chip test capability including the following:

•Debug control/observation (COP)

•Boundary scan (standard IEEE 1149.1a-1993 [JTAG] compliant interface)

•Support for manufacturing test

The COP and boundary scan logic are not used under typical operating conditions. Detailed discussion of the 750GX test functions is beyond the scope of this document. However, sufficient information has been provided to allow the system designer to disable the test functions that would impede normal operation.

The JTAG/COP interface is shown in Figure 8-25. For more information, see IEEE Standard Test Access Port and Boundary Scan Architecture IEEE STD 1149.1a-1993.

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Bus Interface Operation

March 27, 2006

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