User’s Manual

IBM PowerPC 750GX and 750GL RISC Microprocessor

Table 2-26. Store Floating-Point Double Behavior (Page 2 of 2)

FPR Precision

Data Type

Action

 

 

 

 

 

 

Single

SNaN

Store

 

 

 

Double

Normalized

Store

 

 

 

Double

Denormalized

Store

 

 

 

Double

Zero, infinity, QNaN

Store

 

 

 

Double

SNaN

Store

 

 

 

Architecturally, all single-precision and double-precision floating-point numbers are represented in double- precision format within the 750GX. Execution of a store floating-point single (stfs, stfsu, stfsx, stfsux) instruction requires conversion from double to single-precision format. If the exponent is not greater than 896, this conversion requires denormalization. The 750GX supports this denormalization by shifting the mantissa one bit at a time. Anywhere from 1 to 23 clock cycles are required to complete the denormalization, depending upon the value to be stored.

Because of how floating-point numbers are implemented in the 750GX, there is also a case when execution of a store floating-point double (stfd, stfdu, stfdx, stfdux) instruction can require internal shifting of the mantissa. This case occurs when the operand of a store floating-point double instruction is a denormalized single-precision value. The value could be the result of a load floating-point single instruction, a single-precision arithmetic instruction, or a floating round to single-precision instruction. In these cases, shifting the mantissa takes from 1 to 23 clock cycles, depending upon the value to be stored. These cycles are incurred during the store.

2.3.4.4 Branch and Flow-Control Instructions

Some branch instructions can redirect instruction execution conditionally based on the value of bits in the CR. When the processor encounters one of these instructions, it scans the execution pipelines to determine whether an instruction in progress can affect the particular CR bit. If no interlock is found, the branch can be resolved immediately by checking the bit in the CR and taking the action defined for the branch instruction.

Branch Instruction Address Calculation

Branch instructions can alter the sequence of instruction execution. Instruction addresses are always assumed to be word aligned; the PowerPC processors ignore the two low-order bits of the generated branch target address. Branch instructions compute the EA of the next instruction address using the following addressing modes:

•Branch relative

•Branch conditional to relative address

•Branch to absolute address

•Branch conditional to absolute address

•Branch conditional to link register

•Branch conditional to count register

Note: In the 750GX, all branch instructions (b, ba, bl, bla, bc, bca, bcl, bcla, bclr, bclrl, bcctr, bcctrl) and condition register logical instructions (crand, cror, crxor, crnand, crnor, crandc, creqv, crorc, and mcrf) are executed by the branch processing unit (BPU). Some of these instructions can redirect instruction execution conditionally based on the value of bits in the CR. Whenever the CR bits resolve, the branch direction is either marked as correct or mispredicted. Correcting a mispredicted branch requires that the 750GX flush

Programming Model

gx_02.fm.(1.2)

Page 106 of 377

March 27, 2006