
User’s Manual
IBM PowerPC 750GX and 750GL RISC Microprocessor
Table
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60x Bus Specification Command | Transaction | TT0 | TT1 | TT2 | TT3 | TT4 | Snooper; | |
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| Action on Hit | |
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eieio | Address only | 1 | 0 | 0 | 0 | 0 | N/A | |
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External control word write | 1 | 0 | 1 | 0 | 0 | N/A | ||
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TLB Invalidate | Address only | 1 | 1 | 0 | 0 | 0 | N/A | |
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External control word read | 1 | 1 | 1 | 0 | 0 | N/A | ||
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lwarx | Address only | 0 | 0 | 0 | 0 | 1 | N/A | |
reservation set | ||||||||
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Reserved | — | 0 | 0 | 1 | 0 | 1 | N/A | |
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tlbsync | Address only | 0 | 1 | 0 | 0 | 1 | N/A | |
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icbi | Address only | 0 | 1 | 1 | 0 | 1 | N/A | |
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Reserved | — | 1 | X | X | 0 | 1 | N/A | |
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0 | 0 | 0 | 1 | 0 | Flush, cancel reserva- | |||
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0 | 0 | 1 | 1 | 0 | Kill, cancel reservation | |||
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Read | 0 | 1 | 0 | 1 | 0 | Clean or flush | ||
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Burst | 0 | 1 | 1 | 1 | 0 | Flush | ||
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1 | 0 | 0 | 1 | 0 | Flush, cancel reserva- | |||
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Reserved | N/A | 1 | 0 | 1 | 1 | 0 | N/A | |
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1 | 1 | 0 | 1 | 0 | Clean or flush | |||
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Burst | 1 | 1 | 1 | 1 | 0 | Flush | ||
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Reserved | — | 0 | 0 | 0 | 1 | 1 | N/A | |
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Reserved | — | 0 | 0 | 1 | 1 | 1 | N/A | |
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0 | 1 | 0 | 1 | 1 | Clean | |||
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Reserved | — | 0 | 1 | 1 | 1 | 1 | N/A | |
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Reserved | — | 1 | X | X | 1 | 1 | N/A | |
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State | Asserted/ | For memory accesses, these signals, along with the transfer burst (TBST) |
| Negated | signal, indicate the |
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| in Table |
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| size signals are used with the address signals for aligned transfers. |
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| Table |
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| address signals for misaligned transfers. |
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| For external control instructions (eciwx and ecowx), |
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| output bits |
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| form the resource ID |
Signal Descriptions | gx_07.fm.(1.2) |
Page 258 of 377 | March 27, 2006 |