IBM 750GL, 750GX manual 43

User’s Manual

IBM PowerPC 750GX and 750GL RISC Microprocessor

The OEA defines numerous Special-Purpose Registers that serve a variety of functions, such as providing controls, indicating status, configuring the processor, and performing special operations. During normal execution, a program can access the registers shown in Figure 2-1on page 58, depending on the program’s access privilege (supervisor or user, determined by the privilege-level (PR) bit in the MSR). GPRs and FPRs are accessed through operands that are defined in the instructions. Access to registers can be explicit (that is, through the use of specific instructions for that purpose such as Move-to Special-Purpose Register (mtspr) and Move-from Special-Purpose Register (mfspr) instructions) or implicit, as the part of the execution of an instruction. Some registers can be accessed both explicitly and implicitly.

In the 750GX, all SPRs are 32 bits wide. Table 1-2describes the architecture-defined SPRs implemented by the 750GX. In the PowerPC Microprocessor Family: The Programming Environments Manual, these registers are described in detail, including bit descriptions. Section 2.1.1, Register Set, on page 57 describes how these registers are implemented in the 750GX. In particular, that section describes those features defined as optional in the PowerPC Architecture that are implemented on the 750GX.

Table 1-2. Architecture-Defined SPRs Implemented (Page 1 of 2)

Register	Level	Function
LR	User	The Link Register (LR) can be used to provide the branch target address and to hold
		the return address after branch and link instructions.
		The architecture defines eight Block Address Translation Registers (BATs), each imple-
BATs	Supervisor	mented as a pair of 32-bit SPRs. In the 750GX, the BAT facility has been extended to
		include 16 BATs (32 total SPRs), eight for instruction translation and eight for data
		translation. BATs are used to define and configure blocks of memory.
CTR	User	The Count Register (CTR) is decremented and tested by branch-and-count instruc-
		tions.
DABR	Supervisor	The optional Data Address Breakpoint Register (DABR) supports the data address
		breakpoint facility.
DAR	User	The Data Address Register (DAR) holds the address of an access after an alignment or
		data-storage interrupt (DSI) exception.
DEC	Supervisor	The Decrementer Register (DEC) is a 32-bit decrementing counter that provides a way
		to schedule time-delayed exceptions.
DSISR	User	The Data Storage Interrupt Status Register (DSISR) defines the cause of data access
		and alignment exceptions.
		The External Access Register (EAR) controls access to the external access facility
EAR	Supervisor	through the External Control In Word Indexed (eciwx) and External Control Out Word
		Indexed (ecowx) instructions.
PVR	Supervisor	The Processor Version Register (PVR) is a read-only register that identifies the proces-
		sor version and revision level.
SDR1	Supervisor	Storage Description Register 1 (SDR1) specifies the page table address and size used
		in virtual-to-physical page-address translation.
		The Machine Status Save/Restore Register 0 (SRR0) saves the address used for
SRR0	Supervisor	restarting an interrupted program when an rfi instruction executes (also known as
		exceptions).
SRR1	Supervisor	The Machine Status Save/Restore Register 1 (SRR1) is used to save machine status
		on exceptions and to restore machine status when an rfi instruction is executed.

gx_01.fm.(1.2)	PowerPC 750GX Overview
March 27,2006	Page 43 of 377