User’s Manual

IBM PowerPC 750GX and 750GL RISC Microprocessor

These bits allow both uniprocessor and multiprocessor system designs to exploit numerous system-level performance optimizations.

The WIMG attributes are programmed by the operating system for each page and block. The write-through

(W)and caching-inhibited (I) attributes control how the processor performing an access uses its own cache. The memory coherency (M) attribute ensures that coherency is maintained for all copies of the addressed memory location. The guarded memory (G) attribute prevents out-of-order loading and prefetching from the addressed memory location.

The WIMG attributes occupy four bits in the BAT registers for block-address translation and in the PTEs for page-address translation. The WIMG bits are programmed as follows.

•The operating system uses the Move-to Special Purpose Register (mtspr) instruction to program the WIMG bits in the BAT registers for block-address translation. The instruction BAT (IBAT) register pairs do not have a G bit, and all accesses that use the IBAT register pairs are considered not guarded.

•The operating system writes the WIMG bits for each page into the PTEs in system memory as it sets up the page tables.

When an access requires coherency, the processor performing the access must inform the coherency mechanisms throughout the system that the access requires memory coherency. The M attribute determines the kind of access performed on the bus (global or local).

Software must exercise care with respect to the use of these bits if coherent memory support is desired. Careless specification of these bits might create situations that present coherency paradoxes to the processor. In particular, this can happen when the state of these bits is changed without appropriate precautions (such as flushing the pages that correspond to the changed bits from the caches of all processors in the system) or when the address translations of aliased real addresses specify different values for any of the WIMG bits. These coherency paradoxes can occur within a single processor or across several processors. It is important to note that in the presence of a paradox, the operating system software is responsible for correctness.

For data accesses in real-addressing mode (MSR[DR] = 0), the WIMG bits default to '0011' (write back, caching enabled, memory coherent, guarded). For instruction accesses in real-addressing mode (MSR[IR] = 0), the WIMG bits default to '0001' (write back, caching enabled, memory not coherent, guarded).

3.3.2 MEI Protocol

The 750GX data-cache-coherency protocol is a coherent subset of the standard MESI 4-state cache protocol that omits the shared state. The 750GX’s data cache characterizes each 32-byte block it contains as being in one of three MEI states. Addresses presented to the cache are indexed into the cache directory with bits A[20–26], and the upper-order 20 bits from the physical address translation (PA[0–19]) are compared against the indexed cache directory tags. If neither of the indexed tags matches, the result is a cache miss. If a tag matches, a cache hit occurred, and the directory indicates the state of the cache block through two state bits kept with the tag. The three possible states for a cache block in the cache are the modified state (M), the exclusive state (E), and the invalid state (I). The three MEI states are defined in Table 3-1on page 127.

Instruction-Cache and Data-Cache Operation

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March 27, 2006