User’s Manual

IBM PowerPC 750GX and 750GL RISC Microprocessor

the data transactions to memory in order). Note also that all burst writes by the 750GX are performed as nonglobal, and hence do not normally enable snooping, even for address collision purposes. (Snooping might still occur for reservation cancelling purposes.)

3.6.4 Snoop Response to 60x Bus Transactions

There are several bus transaction types defined for the 60x bus. The transactions in Table 3-5correspond to the transfer type signals TT[0–4], which are described in Section 7.2.4.1, Transfer Type (TT[0–4]),on page 256.

The 750GX never retries a transaction in which GBL is not asserted, even if the tags are busy or there is a tag hit. Reservations are snooped regardless of the state of GBL.

Table 3-5. Response to Snooped Bus Transactions (Page 1 of 3)

Snooped Transaction

TT[0–4]

750GX Response

 

 

 

 

 

 

Clean block

00000

No action is taken.

 

 

 

Flush block

00100

No action is taken.

 

 

 

SYNC

01000

No action is taken.

 

 

 

 

 

The kill block operation is an address-only bus transaction initiated when a dcbz or

 

 

dcbi instruction is executed.

 

 

• If the addressed cache block is in the exclusive (E) state, the cache block is

 

 

placed in the invalid (I) state.

Kill block

01100

• If the addressed cache block is in the modified (M) state, the 750GX asserts

 

 

ARTRY and initiates a push of the modified block out of the cache and the

 

 

cache block is placed in the invalid (I) state.

 

 

• If the address misses in the cache, no action is taken.

 

 

Any reservation associated with the address is canceled.

 

 

 

EIEIO

10000

No action is taken.

 

 

 

External control word write

10100

No action is taken.

 

 

 

TLB invalidate

11000

No action is taken.

 

 

 

External control word read

11100

No action is taken.

 

 

 

lwarx reservation set

00001

No action is taken.

 

 

 

Reserved

00101

—

 

 

 

TLBSYNC

01001

No action is taken.

 

 

 

ICBI

01101

No action is taken.

 

 

 

Reserved

1XX01

—

 

 

 

 

 

A write-with-flush operation is a single-beat or burst transaction initiated when a

 

 

caching-inhibited or write-through store instruction is executed.

 

 

• If the addressed cache block is in the exclusive (E) state, the cache block is

 

 

placed in the invalid (I) state.

Write-with-flush

00010

• If the addressed cache block is in the modified (M) state, the 750GX asserts

 

 

ARTRY and initiates a push of the modified block out of the cache, and the

 

 

cache block is placed in the invalid (I) state.

 

 

• If the address misses in the cache, no action is taken.

 

 

Any reservation associated with the address is canceled.

 

 

 

gx_03.fm.(1.2)

Instruction-Cache and Data-Cache Operation

March 27, 2006

Page 143 of 377