User’s Manual
IBM PowerPC 750GX and 750GL RISC Microprocessor
2. Programming Model ..................................................................................................
57
2.1 PowerPC 750GX Processor Register Set .......................................................................................
2.1.1 Register Set ...........................................................................................................................
2.1.2 PowerPC 750GX-Specific Registers ......................................................................................
64
2.1.2.1 Instruction Address Breakpoint Register (IABR) ............................................................
2.1.2.2 Hardware-Implementation-Dependent Register 0 (HID0) ..............................................
65
2.1.2.3 Hardware-Implementation-Dependent Register 1 (HID1) ..............................................
70
2.1.2.4 Hardware-Implementation-Dependent Register 2 (HID2) ..............................................
71
2.1.2.5 Performance-Monitor Registers ......................................................................................
72
2.1.3 Instruction Cache Throttling Control Register (ICTC) ............................................................
77
2.1.4 Thermal-Management Registers (THRMn) ............................................................................
78
2.1.4.1 Thermal-Management Registers 1–2(THRM1–THRM2) ...............................................
2.1.4.2 Thermal-Management Register 3 (THRM3) ...................................................................
79
2.1.4.3 Thermal-Management Register 4 (THRM4) ...................................................................
80
2.1.5 L2 Cache Control Register (L2CR) ........................................................................................
81
2.2 Operand Conventions .....................................................................................................................
82
2.2.1 Data Organization in Memory and Data Transfers ................................................................
2.2.2 Alignment and Misaligned Accesses .....................................................................................
2.2.3 Floating-Point Operand and Execution Models—UISA .........................................................
83
2.2.3.1 Denormalized Number Support ......................................................................................
2.2.3.2 Non-IEEE Mode (Nondenormalized Mode) ....................................................................
2.2.3.3 Time-CriticalFloating-Point Operation ...........................................................................
84
2.2.3.4 Floating-Point Storage Access Alignment ......................................................................
2.2.3.5 Optional Floating-Point Graphics Instructions ................................................................
2.3 Instruction Set Summary .................................................................................................................
86
2.3.1 Classes of Instructions ...........................................................................................................
87
2.3.1.1 Definition of Boundedly Undefined .................................................................................
2.3.1.2 Defined Instruction Class ................................................................................................
2.3.1.3 Illegal Instruction Class ...................................................................................................
88
2.3.1.4 Reserved Instruction Class .............................................................................................
89
2.3.2 Addressing Modes .................................................................................................................
2.3.2.1 Memory Addressing ........................................................................................................
2.3.2.2 Memory Operands ..........................................................................................................
2.3.2.3 Effective Address Calculation .........................................................................................
90
2.3.2.4 Synchronization ..............................................................................................................
2.3.3 Instruction Set Overview ........................................................................................................
91
2.3.4 PowerPC UISA Instructions ...................................................................................................
92
2.3.4.1 Integer Instructions .........................................................................................................
2.3.4.2 Floating-Point Instructions ..............................................................................................
95
2.3.4.3 Load-and-Store Instructions ...........................................................................................
98
2.3.4.4 Branch and Flow-Control Instructions ..........................................................................
106
2.3.4.5 System Linkage Instruction—UISA ..............................................................................
108
2.3.4.6 Processor Control Instructions—UISA .........................................................................
2.3.4.7 Memory Synchronization Instructions—UISA ...............................................................
113
2.3.5 PowerPC VEA Instructions ..................................................................................................
2.3.5.1 Processor Control Instructions—VEA ...........................................................................
2.3.5.2 Memory Synchronization Instructions—VEA ................................................................
114
2.3.5.3 Memory Control Instructions—VEA ..............................................................................
115
2.3.5.4 Optional External Control Instructions ..........................................................................
117
2.3.6 PowerPC OEA Instructions ..................................................................................................
118
750gx_umTOC.fm.(1.2)
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March 27, 2006
