User’s Manual
IBM PowerPC 750GX and 750GL RISC Microprocessor
Another consideration is page table aliasing. If a store hits to a modified cache block but the page table entry is marked write-through (WIMG = 1xxx), then the page has probably been aliased through another page table entry which is marked write-back (WIMG = 0xxx). If this occurs, the 750GX ignores the modified bit in the cache tag. The cache block is updated during the write-through operation, and the block remains in the modified state.
The global (GBL) signal, asserted as part of the address attribute field during a bus transaction, enables the snooping hardware of the 750GX. Address-bus masters assert GBL to indicate that the current transaction is a global access (that is, an access to memory shared by more than one device). If GBL is not asserted for the transaction, that transaction is not snooped by the 750GX. Note that the GBL signal is not asserted for instruction fetches, and that GBL is asserted for all data read or write operations when using real-addressing mode (that is, address translation is disabled).
Normally, GBL reflects the M-bit value specified for the memory reference in the corresponding translation descriptors. Care should be taken to minimize the number of pages marked as global, because the retry protocol enforces coherency and can use considerable bus bandwidth if much data is shared. Therefore, available bus bandwidth decreases as more memory is marked as global.
The 750GX snoops a transaction if the transfer start (TS) and GBL signals are asserted together in the same bus clock (this is a qualified snooping condition). No snoop update to the 750GX cache occurs if the snooped transaction is not marked global. Also, because cache-block castouts and snoop pushes do not require snooping, the GBL signal is not asserted for these operations.
When the 750GX detects a qualified snoop condition, the address associated with the TS signal is compared with the cache tags. Snooping finishes if no hit is detected. If, however, the address hits in the cache, the 750GX reacts according to the MEI protocol shown in Figure 3-4on page 128.
3.3.3 Coherency Precautions in Single-Processor SystemsThe following coherency paradoxes can be encountered within a single-processor system.
•Load or store to a caching-inhibited page (WIMG = x1xx) and a cache hit occurs.
The 750GX ignores any hits to a cache block in a memory space marked caching-inhibited (WIMG = x1xx). The access is performed on the external bus as if there were no hit. The data in the cache is not pushed, and the cache block is not invalidated.
•Store to a page marked write-through (WIMG = 1xxx) and a cache hit occurs to a modified cache block. The 750GX ignores the modified bit in the cache tag. The cache block is updated during the write-through operation, but the block remains in the modified state (M).
Note that when WIM bits are changed in the page tables or BAT registers, it is critical that the cache contents reflect the new WIM bit settings. For example, if a block or page that had allowed caching becomes caching- inhibited, software should ensure that the appropriate cache blocks are flushed to memory and invalidated.
3.3.4 Coherency Precautions in Multiprocessor SystemsThe 750GX’s 3-state coherency protocol permits no data sharing between the 750GX and other caches. All burst reads initiated by the 750GX are performed as read with intent to modify. Burst snoops are interpreted as read with intent to modify or read with no intent to cache. This effectively places all caches in the system into a 3-state coherency scheme. The 4-state caches can share data amongst themselves but not with the 750GX.
gx_03.fm.(1.2) | Instruction-Cache and Data-Cache Operation |
March 27, 2006 | Page 129 of 377 |
