IBM 750GL, 750GX manual 44

User’s Manual

IBM PowerPC 750GX and 750GL RISC Microprocessor

Table 1-2. Architecture-Defined SPRs Implemented (Page 2 of 2)

Register	Level	Function
SPRG0–SPRG3	Supervisor	The general-purpose SPRs (SPRG0–SPRG3) are provided for operating system use.
	User: read	The Time Base Register (TB) is a 64-bit register that maintains the time and date vari-
TB	Supervisor:	able. The TB consists of two 32-bit fields—time-base upper (TBU) and time-base lower
	read/write	(TBL).
		The Integer Exception Register (XER) contains the summary overflow bit, integer carry
XER	User	bit, overflow bit, and a field specifying the number of bytes to be transferred by a Load
		String Word Indexed (lswx) or Store String Word Indexed (stswx) instruction.

Table 1-3describes the SPRs in 750GX that are not defined by the PowerPC Architecture. Section 2.1.2, PowerPC 750GX-Specific Registers, on page 64 gives detailed descriptions of these registers, including bit descriptions.

.

Table 1-3. Implementation-Specific Registers

Register	Level	Function
HID0	Supervisor	The Hardware-Implementation-Dependent Register 0 (HID0) provides checkstop
		enables and other functions.
HID1	Supervisor	The Hardware-Implementation-Dependent Register 1 (HID1) controls the dual PLLs.
HID2	Supervisor	The Hardware-Implementation-Dependent Register 2 (HID2) provides control and sta-
		tus of special cache-related parity functions.
		The Instruction Address Breakpoint Register (IABR) supports instruction address
IABR	Supervisor	breakpoint exceptions. It can hold an address to compare with instruction addresses in
		the IQ. An address match causes an instruction address breakpoint exception.
		The Instruction Cache-Throttling Control Register (ICTC) has bits for controlling the
ICTC	Supervisor	interval at which instructions are fetched into the instruction buffer in the instruction
		unit. This helps control the 750GX’s overall junction temperature.
L2CR	Supervisor	The L2 Cache Control Register (L2CR) is used to configure and operate the L2 cache.
		The Monitor Mode Control Registers (MMCR0–MMCR1) are used to enable various
MMCR0–MMCR1	Supervisor	performance monitoring interrupt functions. UMMCR0–UMMCR1 provide user-level
		read access to MMCR0–MMCR1.
PMC1–PMC4	Supervisor	The Performance-Monitor Counter Registers (PMC1–PMC4) are used to count speci-
		fied events. UPMC1–UPMC4 provide user-level read access to these registers.
		The Sampled Instruction Address Register (SIA) holds the EA of an instruction execut-
SIA	Supervisor	ing at or around the time the processor signals the performance-monitor interrupt con-
		dition. The USIA register provides user-level read access to the SIA.
		THRM1 and THRM2 provide a way to compare the junction temperature against two
THRM1, THRM2	Supervisor	user-provided thresholds. The thermal assist unit (TAU) can be operated so that the
		thermal sensor output is compared to only one threshold, selected in THRM1 or
		THRM2.
THRM3	Supervisor	THRM3 is used to enable the TAU and to control the output sample time.
THRM4	Supervisor	THRM4 provides the temperature offset to junction temperature for accurate operation
		of the thermal assist unit.
UMMCR0–UMMCR1	User	The User Monitor Mode Control Registers (UMMCR0–UMMCR1) provide user-level
		read access to MMCR0–MMCR1.
UPMC1–UPMC4	User	The User Performance-Monitor Counter Registers (UPMC1–UPMC4) provide user-
		level read access to PMC1–PMC4.
USIA	User	The User Sampled Instruction Address Register (USIA) provides user-level read
		access to the SIA register.
PowerPC 750GX Overview		gx_01.fm.(1.2)
Page 44 of 377		March 27,2006