User’s Manual

IBM PowerPC 750GX and 750GL RISC Microprocessor

O

OEA

exception mechanism, 151

memory management specifications, 179 registers, 60

Operand conventions, 82

Operand placement and performance, 233 Operating environment architecture (OEA), 41 Operations

bus operations caused by cache control instructions, 141

instruction cache block fill, 139 read operation, 140

response to snooped bus transactions, 143 single-beat write operations, 311

Overview, 23

PowerPC architecture

operating environment architecture (OEA), 41 user instruction set architecture (UISA), 41 virtual environment architecture (VEA), 41

Priorities, exception, 153 Process switching, 162

Processor control instructions, 108, 113, 118 Program exception, 170

Program order, definition, 210 Programmable power states

doze mode, 337 nap mode, 337 sleep mode, 339

Protection of memory areas no-execute protection, 190 options available, 187 protection violations, 192

PVR (processor version register), 60

P

Page address translation definition, 33

page address translation flow, 202 page size, 196

selection of page address translation, 186, 192 TLB organization, 200

Page history status

cases of dcbt and dcbtst misses, 197 R and C bit recording, 188, 196–199

Page table updates, 207 Performance monitor

event counting, 355 event selecting, 356

performance monitor interrupt, 172, 349 performance monitor SPRs, 350 purposes, 349

registers, 351 warnings, 356

Physical address generation, 179 Pipeline

instruction timing, definition, 210 pipeline stages, 214 pipelined execution unit, 212 superscalar/pipeline diagram, 212

PMC1 and PMC2 registers, 44

PMCn (performance monitor counter) registers, 74, 172, 351

Power and ground signals, 278 Power management

doze mode, 337

dynamic power management, 335 full-power mode, 337

nap mode, 337

programmable power modes, 336 sleep mode, 339

software considerations, 340

Q

QACK (quiescent acknowledge) signal, 273 QREQ (quiescent request) signal, 273 Qualified bus grant, 285

Qualified data bus grant, 302

R

Read operation, 143 Read-atomic operation, 143

Read-with-intent-to-modify operation, 143

Real address (RA), see Physical address generation Real addressing mode (translation disabled)

data accesses, 189, 195 instruction accesses, 189, 195 support for real addressing mode, 180

Referenced (R) bit maintenance recording, 188, 197, 204

Registers implementation-specific

ICTC, 77, 348

L2CR, 81, 329 MMCR0, 72, 172, 351 MMCR1, 74, 172, 351 SIA, 75, 172 THRMn, 78 UMMCR0, 73 UMMCR1, 74 UPMCn, 75

USIA, 76

performance monitor registers, 72 SPR encodings, 112 supervisor-level

BAT registers, 61

750gx_umIX.fm.(1.2)

Index

March 27, 2006

Page 373 of 377