IBM 750GL, 750GX manual 325

User’s Manual

IBM PowerPC 750GX and 750GL RISC Microprocessor

Whenever a way in the set is referenced, the LRU bits are updated. The new value of the LRU bits depends on the old value, which way is currently being accessed, and whether the operation is an invalidation or a load/store. Table 9-2shows the new value of the LRU bits for the various combinations of these variables. An ‘x’ indicates don’t care, while a ‘-’ indicates no change from previous value.

Table 9-2. Modification of LRU Bits

Old LRU	Hit Way	Invalidate	New LRU
00x	none	x	11-
01x	none	x	10-
1x0	none	x	0-1
1x1	none	x	0-0
xxx	0	0	11-
xxx	1	0	10-
xxx	2	0	0-1
xxx	3	0	0-0
xxx	0	1	00-
xxx	1	1	01-
xxx	2	1	1-0
xxx	3	1	1-1

The 4-way set-associative L2 cache can be locked by way as described below. The determination of the new LRU value does not depend on the locked status of the ways. However, the interpretation of the LRU bits shown in Table 9-2does change when one or more ways of the cache are locked.

Any combination of ways can be locked. The effect of locking on the replacement algorithm is that the least recently used of the unlocked ways is chosen for replacement. Table 9-3shows the interpretation of the LRU bits in the presence of one or two locked ways. If three ways are locked, the unlocked way is always replaced, and if all four ways are locked, no replacement takes place. In Table 9-3, bit zero of the lock bits controls whether way 0 is locked, bit one controls whether way 1 is locked, and so forth.

Table 9-3. Effect of Locked Ways on LRU Interpretation (Page 1 of 2)

LRU Bits	Lock Bits	LRU Way
00x	0xxx	0
00x	10xx	1
000	110x	2
001	11x0	3
01x	x0xx	1
01x	01xx	0
010	110x	2
011	11x0	3
1x0	xx0x	2
1x0	xx10	3
100	0x11	0
gx_09.fm.(1.2)		L2 Cache
March 27, 2006		Page 325 of 377