User’s Manual

IBM PowerPC 750GX and 750GL RISC Microprocessor

2.3.4.7 Memory Synchronization Instructions—UISA

Memory synchronization instructions control the order in which memory operations are completed with respect to asynchronous events, and the order in which memory operations are seen by other processors or memory-access mechanisms. See Chapter 3, Instruction-Cache and Data-Cache Operation, on page 121 for additional information about these instructions and about related aspects of memory synchronization. See Table 2-35for a summary.

Table 2-35. Memory Synchronization Instructions—UISA

Name

Mnemonic

Syntax

Implementation Notes

 

 

 

 

 

 

 

 

Load Word and

lwarx

rD,rA,rB

Programmers can use lwarx with stwcx. to emulate common semaphore operations such

Reserve

as test and set, compare and swap, exchange memory, and fetch and add. Both instructions

Indexed

 

 

must use the same EA. Reservation granularity is implementation-dependent. The 750GX

 

 

 

makes reservations on behalf of aligned 32-byte sections of the memory address space. If

 

 

 

 

 

 

the W bit is set, executing lwarx and stwcx. to a page marked write-through does not cause

 

 

 

a DSI exception, but DSI exceptions can result for other reasons. If the location is not word-

Store Word

stwcx.

rS,rA,rB

aligned, an alignment exception occurs.

Conditional

The stwcx. instruction is the only load/store instruction with a valid form if Rc is set. If Rc is

Indexed

 

 

zero, executing stwcx. sets CR0 to an undefined value. In general, stwcx. always causes a

 

 

 

transaction on the external bus and thus operates with slightly worse performance character-

 

 

 

istics than normal store operations.

 

 

 

 

 

 

 

Because it delays subsequent instructions until all previous instructions complete to where

 

 

 

they cannot cause an exception, sync is a barrier against store gathering. Additionally, all

 

 

 

load/store cache/bus activities initiated by prior instructions are completed. Touch load oper-

Synchronize

sync

—

ations (dcbt, dcbtst) must complete address translation, but need not complete on the bus.

 

 

 

If HID0[ABE] = '1', the sync instruction completes after a successful broadcast.

 

 

 

The latency of sync depends on the processor state when it is dispatched and on various

 

 

 

system-level situations. Therefore, frequent use of sync might degrade performance.

 

 

 

 

System designs with an L2 cache should take special care to recognize the hardware signaling caused by a sync bus operation and perform the appropriate actions to guarantee that memory references that can be queued internally to the L2 cache have been performed globally.

See Section 2.3.5.2, Memory Synchronization Instructions—VEA,on page 114 for details about additional memory synchronization (eieio and isync) instructions.

In the PowerPC Architecture, the Rc bit must be zero for most load-and-store instructions. If Rc is set, the instruction form is invalid for sync and lwarx instructions. If the 750GX encounters one of these invalid instruction forms, it sets CR0 to an undefined value.

2.3.5 PowerPC VEA Instructions

The PowerPC virtual environment architecture (VEA) describes the semantics of the memory model that can be assumed by software processes, and includes descriptions of the cache model, cache-control instructions, address aliasing, and other related issues. Implementations that conform to the VEA also adhere to the UISA, but might not necessarily adhere to the OEA.

This section describes additional instructions that are provided by the VEA.

2.3.5.1 Processor Control Instructions—VEA

In addition to the Move-to Condition Register instructions (specified by the UISA), the VEA defines the mftb instruction (user-level instruction) for reading the contents of the Time Base Register. See Chapter 3, Instruction -Cache and Data-Cache Operation, on page 121 for more information.

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Programming Model

March 27, 2006

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