User’s Manual

IBM PowerPC 750GX and 750GL RISC Microprocessor

Table 8-4. Aligned Data Transfers

(Page 2 of 2)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Transfer Size

TSIZ0

TSIZ1

 

TSIZ2

A[29–31]

 

 

Data-Bus Byte Lane(s)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0

1

2

3

4

5

6

 

7

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Word

1

0

 

0

000

x

x

x

x

—

—

—

 

—

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1

0

 

0

100

—

—

—

—

x

x

x

 

x

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Double word

0

0

 

0

000

x

x

x

x

x

x

x

 

x

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Note: The entries with an “x” indicate the byte portions of the requested operand that are read or written during a bus transaction.

 

The entries with a “–” are not required and are ignored during read transactions, and they are driven with undefined data during all write

transactions.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

The 750GX supports misaligned memory operations, although their use can substantially degrade perfor- mance. Misaligned memory transfers address memory that is not aligned to the size of the data being transferred (such as, a word read of an odd byte address). Although most of these operations hit in the primary cache (or generate burst memory operations if they miss), the 750GX interface supports misaligned transfers within a word (32-bit aligned) boundary, as shown in Table 8-5on page 298.

Note: The 4-byte transfer in Table 8-5is only one example of misalignment. As long as the attempted transfer does not cross a word boundary, the 750GX can transfer the data on the misaligned address (for example, a half-word read from an odd byte-aligned address). An attempt to address data that crosses a word boundary requires two bus transfers to access the data.

Due to the performance degradations associated with misaligned memory operations, they are best avoided. In addition to the double-word straddle boundary condition, the address-translation logic can generate substantial exception overhead when the load/store multiple and load/store string instructions access misaligned data. It is strongly recommended that software attempt to align data where possible.

gx_08.fm.(1.2)

Bus Interface Operation

March 27, 2006

Page 297 of 377