User’s Manual

IBM PowerPC 750GX and 750GL RISC Microprocessor

Table 6-9. Load-and-Store Instructions

(Page 2 of 4)

 

 

 

 

 

 

 

 

 

 

 

 

Instruction

Mnemonic

 

Primary

Extended

Unit

Cycles

Serialization

 

Opcode

Opcode

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Load Floating-Point

lfsx

 

31

535

LSU

2:1

—

Single Indexed

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Load Halfword

lha

 

42

—

LSU

2:1

—

Algebraic

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Load Halfword

lhau

 

43

—

LSU

2:1

—

Algebraic with Update

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Load Halfword

lhaux

 

 

 

 

 

 

Algebraic with Update

 

31

375

LSU

2:1

—

Indexed

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Load Halfword

lhax

 

31

343

LSU

2:1

—

Algebraic Indexed

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Load Halfword Byte-

lhbrx

 

31

790

LSU

2:1

—

Reverse Indexed

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Load Halfword and Zero

lhz

 

40

—

LSU

2:1

—

 

 

 

 

 

 

 

 

Load Halfword and Zero

lhzu

 

41

—

LSU

2:1

—

with Update

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Load Halfword and Zero

lhzux

 

31

311

LSU

2:1

—

with Update Indexed

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Load Halfword and Zero

lhzx

 

31

279

LSU

2:1

—

Indexed

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Load Multiple Word

lmw

 

46

—

LSU

2 + n3

Completion, execution

Load String Word

lswi

 

31

597

LSU

2 + n 3

Completion, execution

Immediate

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Load String Word

lswx

 

31

533

LSU

2 + n 3

Completion, execution

Indexed

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Load Word And

lwarx

 

31

20

LSU

3:1

Execution

Reserve Indexed

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Load Word Byte-

lwbrx

 

31

534

LSU

2:1

—

Reverse Indexed

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Load Word and Zero

lwz

 

32

—

LSU

2:1

—

 

 

 

 

 

 

 

 

Load Word and Zero

lwzu

 

33

—

LSU

2:1

—

with Update

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Load Word and Zero

lwzux

 

31

55

LSU

2:1

—

with Update Indexed

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Load Word and Zero

lwzx

 

31

23

LSU

2:1

—

Indexed

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Store Byte

stb

 

38

—

LSU

2:1

—

 

 

 

 

 

 

 

 

Store Byte with Update

stbu

 

39

—

LSU

2:1

—

 

 

 

 

 

 

 

 

Store Byte with Update

stbux

 

31

247

LSU

2:1

—

Indexed

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Store Byte Indexed

stbx

 

31

215

LSU

2:1

—

 

 

 

 

 

 

 

 

1. For cache operations, the first number indicates the latency in finishing a single instruction; the second indicates the throughput for

back-to-back cache operations. Throughput might be larger than the initial latency, as more cycles might be needed to complete

the instruction to the cache, which stays busy keeping subsequent cache operations from executing.

 

2. The throughput number of six cycles for dcbz assumes it is to nonglobal (M = 0) address space. For global address space,

throughput is at least 11 cycles.

 

 

 

 

 

 

3. Load/store multiple/string instruction cycles are represented as a fixed number of cycles plus a variable number of cycles, where n

is the number of words accessed by the instruction.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

gx_06.fm.(1.2)

 

 

 

 

 

 

Instruction Timing

March 27, 2006

 

 

 

 

 

 

Page 245 of 377