IBM 750GL, 750GX 6. Instruction Timing, 6.1 Terminology and Conventions

User’s Manual

IBM PowerPC 750GX and 750GL RISC Microprocessor

6. Instruction Timing

This chapter describes how the PowerPC 750GX microprocessor fetches, dispatches, and executes instructions and how it reports the results of instruction execution. It gives detailed descriptions of how the 750GX’s execution units work, and how those units interact with other parts of the processor, such as the instruction- fetching mechanism, register files, and caches. It gives examples of instruction sequences, showing potential bottlenecks and how to minimize their effects. Finally, it includes tables that identify the unit that executes each instruction implemented on the 750GX, the latency for each instruction, and other information that is useful for the assembly language programmer.

6.1 Terminology and Conventions

This section provides an alphabetical glossary of terms used in this chapter. These definitions are provided as a review of commonly used terms and to point out specific ways these terms are used in this chapter.

Branch prediction	The process of guessing whether a branch will or will not be taken. Such predic-
	tions can be correct or incorrect. The term ‘predicted’ as it is used here does not
	imply that the prediction is correct (successful). Instructions along the predicted
	path are fetched and dispatched to their respective execution units conditionally
	and can reach the completion unit. However, these instructions must first be vali-
	dated by the branch-resolution process before they can be retired.
	The PowerPC Architecture defines a means for static branch prediction as part of
	the instruction encoding. The 750GX processor implements two types of dynamic
	branch prediction. See Section 6.4.1.2, Branch Instructions and Completion, on
	page 227.
Branch resolution	The determination of the path that a branch instruction must take. If a branch
	prediction and branch resolution occur on the same cycle, the processor simply
	fetches instructions on the correct path as determined by the branch instruction.
	For predicted branches, branch resolution must determine if the prediction was
	correct. If the prediction was correct, all speculatively fetched instructions that have
	been passed to their execution units are validated. If the prediction was wrong, the
	speculatively fetched instructions must be invalidated (flushed), and instruction
	fetching must resume along the other path for the branch instruction.
Completion	Completion occurs when an instruction has finished executing, and its results are
	stored in a Rename Register allocated to it by the dispatch unit. These results are
	available to subsequent instructions or to previously predicted branches.
Dispatch	The process of moving an instruction from the instruction queue to an execution
	unit. In the 750GX processor, the dispatch unit can process up to three instruction
	in a single cycle if one of the three is a branch. For the non-branch-type instruc-
	tions, the dispatch must do a partial decode to determine the type of instruction in
	order to pass it to the respective execution unit. Also, a Rename Register and a
	place in the completion queue must be reserved; otherwise, a stall occurs. If a
	branch updates either the Link Register (LR) or Count Register (CTR), it must also
	be allocated to a completion queue entry.
Fall-through	A not-taken branch.
gx_06.fm.(1.2)	Instruction Timing
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