User’s Manual

IBM PowerPC 750GX and 750GL RISC Microprocessor

2.3.2.3 Effective Address Calculation

An effective address is the 32-bit sum computed by the processor when executing a memory-access or branch instruction or when fetching the next sequential instruction. For a memory-access instruction, if the sum of the effective address and the operand length exceeds the maximum effective address, the memory operand is considered to wrap around from the maximum effective address through effective address 0, as described in the following paragraphs.

Effective address computations for both data and instruction accesses use 32-bit signed two’s complement binary arithmetic. A carry from bit 0 and overflow are ignored.

Load-and-store operations have the following modes of effective address generation:

•EA = (rA0) + offset (including offset = 0) (register indirect with immediate index)

•EA = (rA0) + rB (register indirect with index)

See Integer Load-and-Store Address Generation on page 99 for a detailed description of effective address generation for load-and-store operations.

Branch instructions have three categories of effective address generation:

•Immediate

•Link register indirect

•Count register indirect

2.3.2.4 Synchronization

The synchronization described in this section refers to the state of the processor that is performing the synchronization.

Context Synchronization

The System Call (sc) and Return from Interrupt (rfi) instructions perform context synchronization by allowing previously issued instructions to complete before performing a change in context. Execution of one of these instructions ensures the following:

•No higher-priority exception exists (sc).

•All previous instructions have completed to a point where they can no longer cause an exception. If a prior memory-access instruction causes direct-store error exceptions, the results are guaranteed to be determined before this instruction is executed.

•Previous instructions complete execution in the context (privilege, protection, and address translation) under which they were issued.

•The instructions following the sc or rfi instruction execute in the context established by these instructions.

Execution Synchronization

An instruction is execution synchronizing if all previously initiated instructions appear to have completed before the instruction is initiated, or in the case of sync and isync, before the instruction completes. For example, the Move-to Machine State Register (mtmsr) instruction is execution synchronizing. It ensures that all preceding instructions have completed execution and cannot cause an exception before the instruction executes, but does not ensure that subsequent instructions execute in the newly established environment.

Programming Model

gx_02.fm.(1.2)

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March 27, 2006