IBM 750GL, 750GX manual 6

User’s Manual
IBM PowerPC 750GX and 750GL RISC Microprocessor
4.2 Exception Recognition and Priorities .............................................................................................	153
4.3 Exception Processing ....................................................................................................................	156
4.3.1 Machine Status Save/Restore Register 0 (SRR0) ...............................................................	156
4.3.2 Machine Status Save/Restore Register 1 (SRR1) ...............................................................	157
4.3.3 Machine State Register (MSR) ............................................................................................	158
4.3.4 Enabling and Disabling Exceptions ......................................................................................	160
4.3.5 Steps for Exception Processing ...........................................................................................	160
4.3.6 Setting MSR[RI] ...................................................................................................................	161
4.3.7 Returning from an Exception Handler ..................................................................................	161
4.4 Process Switching .........................................................................................................................	162
4.5 Exception Definitions .....................................................................................................................	162
4.5.1 System Reset Exception (0x00100) .....................................................................................	163
4.5.1.1 Soft Reset .....................................................................................................................	164
4.5.1.2 Hard Reset ...................................................................................................................	164
4.5.2 Machine-Check Exception (0x00200) ..................................................................................	167
4.5.2.1 Machine-Check Exception Enabled (MSR[ME] = 1) .....................................................	168
4.5.2.2 Checkstop State (MSR[ME] = 0) ..................................................................................	169
4.5.3 DSI Exception (0x00300) .....................................................................................................	169
4.5.4 ISI Exception (0x00400) .......................................................................................................	169
4.5.5 External Interrupt Exception (0x00500) ...............................................................................	169
4.5.6 Alignment Exception (0x00600) ...........................................................................................	170
4.5.7 Program Exception (0x00700) .............................................................................................	170
4.5.8 Floating-Point Unavailable Exception (0x00800) .................................................................	171
4.5.9 Decrementer Exception (0x00900) ......................................................................................	171
4.5.10 System Call Exception (0x00C00) .....................................................................................	171
4.5.11 Trace Exception (0x00D00) ...............................................................................................	171
4.5.12 Floating-Point Assist Exception (0x00E00) ........................................................................	171
4.5.13 Performance-Monitor Interrupt (0x00F00) .........................................................................	172
4.5.14 Instruction Address Breakpoint Exception (0x01300) ........................................................	173
4.5.15 System Management Interrupt (0x01400) .........................................................................	173
4.5.16 Thermal-Management Interrupt Exception (0x01700) .......................................................	174
4.5.17 Data Address Breakpoint Exception ..................................................................................	175
4.5.17.1 Data Address Breakpoint Register (DABR) ................................................................	175
4.5.18 Soft Stops ..........................................................................................................................	175
4.5.19 Exception Latencies ...........................................................................................................	176
4.5.20 Summary of Front-End Exception Handling .......................................................................	176
4.5.21 Timer Facilities ...................................................................................................................	177
4.5.22 External Access Instructions ..............................................................................................	177
5. Memory Management ..............................................................................................	179
5.1 MMU Overview ..............................................................................................................................	179
5.1.1 Memory Addressing .............................................................................................................	181
5.1.2 MMU Organization ...............................................................................................................	181
5.1.3 Address-Translation Mechanisms ........................................................................................	186
5.1.4 Memory-Protection Facilities ................................................................................................	187
5.1.5 Page History Information .....................................................................................................	188
5.1.6 General Flow of MMU Address Translation .........................................................................	189
5.1.6.1 Real-Addressing Mode and Block-Address-Translation Selection ...............................	189
5.1.6.2 Page-Address-Translation Selection ............................................................................	190
5.1.7 MMU Exceptions Summary .................................................................................................	192
	750gx_umTOC.fm.(1.2)
Page 6 of 377	March 27, 2006