IBM 750GL, 750GX manual 112

User’s Manual

IBM PowerPC 750GX and 750GL RISC Microprocessor

Encodings for the 750GX-specific SPRs are listed in Table 2-34.

Table 2-34. SPR Encodings for 750GX-Defined Registers (mfspr)

		1
Register Name		SPR		Access	mfspr/mtspr
	Decimal	SPR[5–9]	SPR[0–4]
DABR	1013	11111	10101	User	Both
HID0	1008	11111	10000	Supervisor	Both
HID1	1009	11111	10001	Supervisor	Both
HID2	1016	11111	11000	Supervisor	Both
IABR	1010	11111	10010	Supervisor	Both
ICTC	1019	11111	11011	Supervisor	Both
L2CR	1017	11111	11001	Supervisor	Both
MMCR0	952	11101	11000	Supervisor	Both
MMCR1	956	11101	11100	Supervisor	Both
PMC1	953	11101	11001	Supervisor	Both
PMC2	954	11101	11010	Supervisor	Both
PMC3	957	11101	11101	Supervisor	Both
PMC4	958	11101	11110	Supervisor	Both
Reserved2	921–924			Supervisor
SIA	955	11101	11011	Supervisor	Both
THRM1	1020	11111	11100	Supervisor	Both
THRM2	1021	11111	11101	Supervisor	Both
THRM3	1022	11111	11110	Supervisor	Both
THRM4	920	11100	11000	Supervisor	mfspr
UMMCR0	936	11101	01000	User	mfspr
UMMCR1	940	11101	01100	User	mfspr
UPMC1	937	11101	01001	User	mfspr
UPMC2	938	11101	01010	User	mfspr
UPMC3	941	11101	01101	User	mfspr
UPMC4	942	11101	01110	User	mfspr
USIA	939	11101	01011	User	mfspr

Note:

1.The order of the two 5-bit halves of the SPR number is reversed compared with actual instruction coding.

For mtspr and mfspr instructions, the SPR number coded in assembly language does not appear directly as a 10-bit binary num- ber in the instruction. The number coded is split into two 5-bit halves that are reversed in the instruction, with the high-order 5 bits appearing in bits 16–20 of the instruction and the low-order 5 bits in bits 11–15.

2.These registers are reserved for future use and the contents should not be changed or reset.

Programming Model	gx_02.fm.(1.2)
Page 112 of 377	March 27, 2006