User’s Manual

IBM PowerPC 750GX and 750GL RISC Microprocessor

Figure 6-9. Branch Completion

Branch Completion

(LR/CTR Write-Back)

 

Clock 0

Clock 1

Clock 2

Clock 3

 

 

 

 

 

 

 

 

IQ5

add5

 

 

 

 

 

 

 

 

 

 

 

 

 

 

IQ4

add4

 

 

 

 

 

 

 

 

 

 

 

 

 

 

IQ3

add3

 

add5

 

add7

 

add9

 

 

 

 

 

 

 

 

IQ2

bc

 

add4

 

add6

 

add8

 

 

 

 

 

 

 

 

IQ1

add2

 

add3

 

add5

 

add7

 

 

 

 

 

 

 

 

IQ0

add1

 

bc

 

add4

 

add6

CQ5

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CQ4

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CQ3

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CQ2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CQ1

 

 

 

 

 

 

 

 

 

add2

 

add3

 

add5

CQ0

 

 

 

 

 

 

 

 

 

add1

 

bc

 

add4

 

 

 

 

 

 

 

 

In this example, the Branch Conditional (bc) instruction is encoded to decrement the CTR. It is predicted as not-taken in clock cycle 0. In clock cycle 2, bc and add3 are both dispatched. In clock cycle 3, the architected CTR is updated, and the bc instruction is retired from the completion queue.

6.4.1.3 Branch Prediction and Resolution

The 750GX supports the following two types of branch prediction:

•Static branch prediction—This is defined by the PowerPC Architecture as part of the encoding of branch instructions.

•Dynamic branch prediction—This is a processor-specific mechanism implemented in hardware (in partic- ular the branch history table, or BHT) that monitors branch instruction behavior and maintains a record from which the next occurrence of the branch instruction is predicted.

When a conditional branch cannot be resolved due to a CR data dependency, the BPU predicts whether it will be taken, and instruction fetching proceeds down the predicted path. If the branch prediction resolves as incorrect, the instruction queue and all subsequently executed instructions are purged, instructions executed prior to the predicted branch are allowed to complete, and instruction fetching resumes down the correct path.

The 750GX executes through two levels of prediction. Instructions from the first unresolved branch can execute, but they cannot be retired until the branch is resolved. If a second branch instruction is encountered in the predicted instruction stream, it can be predicted and instructions can be fetched, but not executed, from the second branch. No action can be taken for a third branch instruction until at least one of the two previous branch instructions is resolved.

The number of instructions that can be executed after the issue of a predicted branch instruction is limited by the fact that no instruction executed after a predicted branch can actually update (be retired) the register files or memory until the branch is resolved. That is, instructions can be issued and executed, but cannot be retired from the completion unit. When an instruction following a predicted branch completes execution, it

Instruction Timing

gx_06.fm.(1.2)

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March 27, 2006