Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor—
Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
DM September 2006
10 Order Number: 252480-006US
11.2.1 Monitored Events South AHB and North AHB............................................ 375
11.2.2 Monitored SDRAM Events.......................................................................377
11.2.3 Cycle Count.........................................................................................377
11.3 Register Descriptions........................................................................................378
11.3.1 Event Select Register............................................................................378
11.3.2 PMU Status Register (PSR).....................................................................381
11.3.3 Programmable Event Counters (PEC1).....................................................381
11.3.4 Programmable Event Counters (PEC2).....................................................382
11.3.5 Programmable Event Counters (PEC3).....................................................382
11.3.6 Programmable Event Counters (PEC4).....................................................382
11.3.7 Programmable Event Counters (PEC5).....................................................383
11.3.8 Programmable Event Counters (PEC6).....................................................383
11.3.9 Programmable Event Counters (PEC7).....................................................384
11.3.10Previous Master/Slave Register (PSMR) ...................................................384
12.0 General Purpose Input/Output (GPIO)..................................................................386
12.1 Using GPIO as Inputs/Outputs...........................................................................386
12.2 Using GPIO as Interrupt Inputs..........................................................................387
12.3 Using GPIO 14 and GPIO 15 as Clocks................................................................389
12.4 Register Description.........................................................................................391
12.4.1 GPIO Output Register............................................................................391
12.4.2 GPIO Output Enable Register..................................................................392
12.4.3 GPIO Input Register..............................................................................392
12.4.4 GPIO Interrupt Status Register...............................................................393
12.4.5 GP Interrupt Type Register 1..................................................................393
12.4.6 GPIO Interrupt Type Register 2...............................................................394
12.4.7 GPIO Clock Register..............................................................................395
13.0 Interrupt Controller...............................................................................................398
13.1 Interrupt Priority .............................................................................................398
13.2 Assigning FIQ or IRQ Interrupts.........................................................................399
13.3 Enabling and Disabling Interrupts ......................................................................399
13.4 Reading Interrupt Status ..................................................................................400
13.5 Interrupt Controller Register Description.............................................................401
13.5.1 Interrupt Status Register.......................................................................402
13.5.2 Interrupt-Enable Register ......................................................................404
13.5.3 Interrupt Select Register........................................................................404
13.5.4 IRQ Status Register ..............................................................................404
13.5.5 FIQ Status Register...............................................................................404
13.5.6 Interrupt Priority Register......................................................................405
13.5.7 IRQ Highest-Priority Register..................................................................405
13.5.8 FIQ Highest-Priority Register........ ..........................................................406
14.0 Timers...................................................................................................................408
14.1 Watch-Dog Timer.............................................................................................408
14.2 Time-Stamp Timer...........................................................................................409
14.3 General-Purpose Timers ...................................................................................409
14.4 Timer Register Definition..................................................................................411
14.4.1 Time-Stamp Timer................................................................................411
14.4.2 General-Purpose Timer 0.......................................................................411
14.4.3 General-Purpose Timer 0 Reload.............................................................412
14.4.4 General-Purpose Timer 1.......................................................................412
14.4.5 General-Purpose Timer 1 Reload.............................................................413
14.4.6 Watch-Dog Timer .................................................................................413
14.4.7 Watch-Dog Enable Register....................................................................414
14.4.8 Watch-Dog Key Register........................................................................414