Intel IXC1100, IXP42X 13.2 Assigning FIQ or IRQ Interrupts, 13.3 Enabling and Disabling Interrupts

Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
September 2006 DM
Order Number: 252480-006US 399
Interrupt Controller—Intel® IXP42X product line and IXC1100 control plane processors
pattern to the assignments above for the first eight interrupts with the last interrupt
priority assignment being bits 21 through 23 of the interrupt priority register assigning
a priority value to interrupt 7.
The 3-bit interrupt priorities for each of the first eight interrupts can take on a value
from 0 to 7. A value of 0 — located the 3-bit interrupt priority register for each of the
first eight interrupts — signifies the highest priority interrupt. A value of 7 — located
the 3-bit interrupt priority register for each of the first eight interrupts — signifies the
lowest priority interrupt. In the case of two interrupts being assigned the same priority,
the interrupts natural priority will assign who has the highest priority.
For example, interrupt number 1 and interrupt number 3 both have a value of 0 —
written as their 3-bit interrupt priorities. Interrupt number 1 would take priority over
interrupt number 3 due to their individual natural priorities.
The priorities assigned to each of the 3-bit interrupt priorities for the first eight
interrupts will be set to a value of the corresponding interrupt number (interrupt
number 0 gets assigned a value of 0 in the associated 3-bit interrupt priority register,
interrupt number 1 gets assigned a value of 1, etc.) when receiving a reset. Therefore,
allowing natural priorities to be the default after a reset.
13.2 Assigning FIQ or IRQ Interrupts
The IXP42X product line and IXC1100 control plane processors Interrupt Controller
provide the capability to assign each interrupt as an FIQ or an IRQ interrupt. As
discussed earlier, the Intel XScale processor only receives a single FIQ interrupt signal
and a single IRQ interrupt signal.
The Interrupt Controller allows multiple interrupts to be sent to the Intel XScale
processor as either FIQ interrupts or IRQ interrupts. Each interrupt may be assigned as
an FIQ interrupt or an IRQ interrupt but never both. The interrupts are assigned as an
FIQ interrupt or an IRQ interrupt by writing bits in the interrupt select register
(INTR_SEL).
The Interrupt Select Register is a 32-bit register that assigns each of the 32 interrupts
to as an FIQ interrupt or an IRQ interrupt. Bit 0 of the Interrupt Select Register
corresponds to interrupt number 0 (WAN/Voice NPE). Bit 31 of the Interrupt Select
Register corresponds to interrupt number 31 (Software Interrupt 1).
Logic 1 written to a bit in the Interrupt Select Register will assign the corresponding
interrupt number as an FIQ interrupt. Writing logic 0 to the same bit in the Interrupt
Select Register will assign the corresponding interrupt number as an IRQ interrupt.
For example, the Interrupt Select Register is written with a hexadecimal value of
0x00000005. The result of this write would set interrupt number 0 (WAN/Voice NPE) as
an FIQ and interrupt number 2 (Ethernet NPE B) as an FIQ.
All other interrupt numbers would be assigned as IRQ interrupts. All interrupts are
assigned as IRQ interrupts upon receiving a reset.
13.3 Enabling and Disabling Interrupts
The interrupts on the IXP42X product line and IXC1100 control plane processors can be
individually enabled or disabled by writing to the Interrupt-Enable Register (INTR_EN).
By disabling an interrupt, the Intel XScale processor will not be interrupted by either
the FIQ interrupt signal or the IRQ interrupt signal when an interrupt occurs on the
corresponding disabled interrupt number.