Intel IXC1100, IXP42X 21.0 AHB Queue Manager (AQM)

Intel® IXP42X product line and IXC1100 control plane processors—AHB Queue Manager (AQM)
Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
DM September 2006
556 Order Number: 252480-006US
21.0 AHB Queue Manager (AQM)
The purpose of this chapter is to outline the functionality of the AHB Queue Manager
(AQM) which helps users to better understand the software and hardware architecture.
The Intel® IXP400 Software manages these queues.
21.1 Overview
The AHB Queue Manager (AQM) provides queue functionality for various internal
blocks. It maintains the queues as circular buffers in an embedded 8KB SRAM. It also
implements the status flags and pointers required for each queue.
The AQM manages 64 independent queues. Each queue is configurable for buffer and
entry size. Additionally status flags are maintained for each queue.
The AQM interfaces include an AHB interface to the NPEs and Intel XScale® Processor
(or any other AHB bus master), a Flag Bus interface, an event bus (to the NPE
condition select logic) and two interrupts to the Intel XScale processor. The AHB
interface is used for configuration of the AQM and provides access to queues, queue
status and SRAM. Individual queue status for queues 0-31 is communicated to the
NPEs via the flag bus. Combined queue status for queues 32-63 are communicated to
the NPEs via the event bus. The two interrupts, one for queues 0-31 and one for
queues 32-63, provide status interrupts to the Intel XScale processor.
Read or write entries to a queue, will be accomplished by performing AHB read/write
accesses to any of the corresponding Queue Access Register addresses. The AQM will
intercept these accesses, since no physical data resides at these addresses, and lookup
the appropriate queue pointer to perform the requested read or write. Upon a read or
write access to a queue, the pointers and status for the queue are updated as needed.
Further detail is given in the following sections.
21.2 Feature List
• Provides queue functionality for NPEs and Intel XScale processor
• Manages 64 independent queues
• Implements queues as FIFOs with circular buffer rotation in SRAM
• Implements read/write pointers for each queue in SRAM
• Programmable queue entry size supported (i.e., queues may be configured for 1, 2,
or 4 word entries)
• Programmable queue size supported (i.e., queues may be configured for 16, 32, 64
or 128 word buffer)
• Maintains empty (E), nearly empty (NE), nearly full (NF), and full (F) status flags
on each of the queues 0-31
• Programmable queue watermarks for assessing NE and NF queue status flags
• Provides status flag information, E, NE, F and NF, for queues 0-31 to the NPEs via a
common Flag Bus