Intel IXC1100, IXP42X - page 282

Intel® IXP42X product line and IXC1100 control plane processors—SDRAM Controller
Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
DM September 2006
282 Order Number: 252480-006US
Writing hexadecimal value 0x00000000 to address location 0xCC000008 will cause a
Mode Register Set command to be initiated. See the chosen SDRAM Memory vendor’s
datasheet for Mode-Register-Set Timing with CAS to data delay of 2 to view the
signaling associated with this command.
Writing hexadecimal value 0x00000001 to address location 0xCC000008 will cause a
Mode Register Set command to be initiated. See the chosen SDRAM Memory vendor’s
datasheet for Mode-Register-Set Timing with CAS to data delay of 3 to view the
signaling associated with this command.
Writing hexadecimal value 0x00000002 to address location 0xCC000008 will cause a
Precharge All command to be initiated. See the chosen SDRAM Memory vendor’s
datasheet for Precharge-All Timing, to view the signaling associated with this
command.
Writing hexadecimal value 0x00000003 to address location 0xCC000008 will cause a
NOP command to be initiated. See the chosen SDRAM Memory vendor’s datasheet for
NOP Timing to view the signaling associated with this command.
Writing hexadecimal value 0x00000004 to address location 0xCC000008 will cause a
Auto-Refresh command to be initiated. See the chosen SDRAM Memory vendor’s
datasheet for Auto-Refresh Timing to view the signaling associated with this command.
Writing hexadecimal value 0x00000005 to address location 0xCC000008 will cause a
Burst Terminate command to be initiated. See the chosen SDRAM Memory vendor’s
datasheet for Burst Terminate Timing to view the signaling associated with this
command.
Tabl e 110 shows the values contained on the control signals for each command that is
issued using the SDRAM Instruction Register (SDR_IR).
Auto-Refresh 100 Used to produce a refresh command to the SDRAM to avoid loss of data. The times between successive refresh commands is a function of the
SDRAM that is chosen.
Burst Terminate 101 A command issued to the SDRAM to terminate a current fixed length
burst.
(Reserved) 110 Writing to this location will cause undetermined results.
(Reserved) 111 Writing to this location will cause undetermined results.
Table 109. SDRAM Command Description (Sheet 2 of 2)
Command Name SDR_IR[2:
0] Description
Table 110. SDRAM I/O For Various Commands
Command SDR_IR[2:0
]SDR_CS_N SDR_RAS_N SDR_CAS_N SDR_WE_N SDR_DQM SDR_ADDR
MODE-REGISTER-SET 000 0 0 0 0 X CODE
MODE-REGISTER-SET 001
PRECHARGE-ALL 010 0 0 1 0 X CODE
NOP 011 0 1 1 1 X X
AUTO-REFRESH 100 0 0 0 1 X X
BURST TERMINATE 101 0 1 1 0 X X