Intel IXC1100, IXP42X 2.3 Internal Bus, 2.4 MII Interfaces, 2.5 AHB Queue Manager

Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
September 2006 DM
Order Number: 252480-006US 39
Overview of Product Line—Intel® IXP42X product line and IXC1100 control plane processors
2.3 Internal Bus
The internal bus architecture of the Intel XScale processor is designed to allow parallel
processing to occur and isolate bus utilization based on particular traffic patterns. The
bus is segmented into three major buses: the North AHB, the South AHB, and the APB.
The North AHB is a 133.32 MHz, 32-bit bus that can be mastered by the WAN NPE or
both of the Ethernet NPEs. The targets of the North AHB can be the SDRAM or the AHB/
AHB Bridge.
The AHB/AHB Bridge will allow access by the NPEs to the peripherals and internal
targets on the South AHB. Data transfers by the NPEs on the North AHB to the South
AHB are targeted predominately to the queue manager. Transfers to the AHB/AHB
Bridge may be “posted” when writing or “split” when reading. This allows control of the
North AHB to be given to another master on the North AHB and enables the bus to
achieve maximum efficiency.
Transfers to the AHB/AHB Bridge are considered to be small and infrequent relative to
the traffic passed between the NPEs on the North AHB and the SDRAM.
The South AHB is a 133.32 MHz, 32-bit bus that can be mastered by the Intel XScale
processor, PCI Controller DMA engines, AHB/AHB Bridge, and the AHB/APB Bridge. The
targets of the South AHB can be the SDRAM, PCI Interface, Queue Manager, or the
APB/AHB Bridge. Accessing across the APB/AHB allows interfacing to peripherals
attached to the APB.
The APB is a 66.66 MHz, 32-bit bus that can be mastered by the AHB/APB Bridge only.
The targets of the APB can be the High-Speed UART Interface, Console UART Interface,
USB v1.1 interface, all NPEs, the Performance Monitoring Unit (PMU), Interrupt
Controller, General-Purpose Input/Output (GPIO), and timers. The APB interface to the
NPEs are used for code download and part configuration.
For more information, see Section 5.0, “Internal Bus” on page204.
2.4 MII Interfaces
Two industry-standard Media Independent Interfaces (MII) are integrated into the
IXP42X product line and IXC1100 control plane processors with separate Media Access
Controllers and Network Processing Engines. This enables parallel processing of data
traffic on the interfaces and off loading of processing overhead required by the Intel
XScale processor.
The IXP42X product line and IXC1100 control plane processors are compliant with the
IEEE, 802.3 specification.
2.5 AHB Queue Manager
The AHB Queue Manager (AQM) provides queue functionality for various internal
blocks. It maintains the queues as circular buffers in an embedded 8KB SRAM. It also
implements the status flags and pointers required for each queue.
The AQM manages 64 independent queues. Each queue is configurable for buffer and
entry size. Additionally status flags are maintained for each queue.
The AQM interfaces include an Advanced High-performance Bus (AHB) interface to the
NPEs and Intel XScale processor (or any other AHB bus master), a Flag Bus interface,
an event bus (to the NPE condition select logic) and two interrupts to the Intel XScale
processor. The AHB interface is used for configuration of the AQM and provides access
to queues, queue status and SRAM. Individual queue status for queues 0-31 is