Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
September 2006 DM
Order Number: 252480-006US 373
Internal Bus Performance Monitoring Unit (IBPMU)—Intel® IXP42X product line and IXC1100
control plane processors
The most-significant bit of each three-bit programmable event counter configuration
register will select if the programmable event counter is to read an occurrence event or
a duration event.
A value of logic 1 — in the most-significant bit of the programmable event counter’s
configuration register (for example, bit 22 for PEC1) — will indicate that the
programmable event counter is to capture a predefined duration event when in South
AHB or North AHB monitoring mode or a page miss when in SDRAM monitoring mode.
A value of logic 0 — in the most-significant bit of the programmable event counter
configuration register — will indicate that the programmable event counter is to
capture a predefined occurrence event when in South AHB or North AHB monitoring
mode or a page hit when in SDRAM monitoring mode.
The least-significant two bits of each of the programmable event counter’s event select
register will indicate the specific event to capture. For a list of possible captured events,
see Section 11.3.1, “Event Select Register” on page 378.
In addition to the seven 3-bit registers contained within the event select register, there
is a 2-bit register — that is the least significant two bits of the Event Select Register
(bits 1 and 0) — that contains the mode select of the programmable event counters.
The mode select will be used to select the mode of operation that the IBPMU is
executing in.
The mode that is selected will be valid across all of the programmable event counters.
That means the South AHB, North AHB, and SDRAM interfaces must be measured
independently. The four modes of operation are:
The mode selection is shown in Tabl e 139:
The programmable event counters will be set to 0 after exiting from the halt mode and
going into any other mode. Entering halt mode from any other mode causes all
programmable event counters to halt at the same time, allowing a snapshot in time to
be read across all of the programmable event counters. All programmable event
counters will be reset and started whenever a new value is written to the ESR and the
mode that is written is not HALT. The Event Select register will be set to all 0s, after a
reset signal is received.
11.2 Using the IBPMU
The IBPMU is designed to allow efficient, real-time collection of statistical information
regarding internal bus and SDRAM acquisitions. This enables a designer to tune the
execution of the software running on the Intel XScale processor to achieve maximum
performance.
• Halt • South AHB Monitoring
• North AHB Monitoring • SDRAM Monitoring
Table 139. IBPMU Mode Selection Operation
Mode Bits
(Event Select Register Bits 1 and 0) Mode of Operation
00 Halt
01 South AHB
10 North AHB
11 SDRAM