Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
September 2006 DM
Order Number: 252480-006US 3
—Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
Contents
1.0 Introduction............................................................................................................26
1.1 About This Document.........................................................................................26
1.1.1 How to Read This Document....................................................................26
1.2 Other Relevant Documents.................................................................................26
1.3 Terminology and Conventions.............................................................................26
1.3.1 Number Representation...........................................................................26
1.3.2 Acronyms and Terminology......................................................................27
2.0 Overview of Product Line........................................................................................30
2.1 Intel XScale® Microarchitecture Processor ............................................................35
2.1.1 Intel XScale® Processor Overview ............................................................36
2.1.1.1 ARM* Compatibility . ..................................................................36
2.1.1.2 Multiply/Accumulate (MAC)........................................................36
2.1.1.3 Memory Management................................................................37
2.1.1.4 Instruction Cache......................................................................37
2.1.1.5 Branch Target Buffer.................................................................37
2.1.1.6 Data Cache..............................................................................37
2.1.1.7 Intel XScale® Processor Performance Monitoring...........................38
2.2 Network Processor Engines (NPE)........................................................................38
2.3 Internal Bus .....................................................................................................39
2.4 MII Interfaces...................................................................................................39
2.5 AHB Queue Manager..........................................................................................39
2.6 UTOPIA 2.........................................................................................................40
2.7 USB v1.1 .................................................................................. .. .. ...................40
2.8 PCI..................................................................................................................40
2.9 Memory Controller.............................................................................................40
2.10 Expansion Bus..................................................................................................41
2.11 High-Speed Serial Interfaces...............................................................................41
2.12 Universal Asynchronous Receiver Transceiver........................................................42
2.13 GPIO...............................................................................................................42
2.14 Interrupt Controller...........................................................................................42
2.15 Timers.............................................................................................................42
2.16 JTAG...............................................................................................................43
3.0 Intel XScale® Processor...........................................................................................44
3.1 Memory Management Unit..................................................................................44
3.1.1 Memory Attributes..................................................................................45
3.1.1.1 Page (P) Attribute Bit................................................................45
3.1.1.2 Cacheable (C), Bufferable (B), and eXtension (X) Bits....................45
3.1.2 Interaction of the MMU, Instruction Cache, and Data Cache .........................47
3.1.3 MMU Control..........................................................................................48
3.1.3.1 Invalidate (Flush) Operation.......................................................48
3.1.3.2 Enabling/Disabling....................................................................48
3.1.3.3 Locking Entries.........................................................................49
3.1.3.4 Round-Robin Replacement Algorithm...........................................51
3.2 Instruction Cache..............................................................................................52
3.2.1 Operation When Instruction Cache is Enabled.............................................52
3.2.1.1 Instruction-Cache ‘Miss’.............................................................53
3.2.1.2 Instruction-Cache Line-Replacement Algorithm.............................54
3.2.1.3 Instruction-Cache Coherence......................................................55
3.3 Branch Target Buffer .........................................................................................58
3.3.1 Branch Target Buffer (BTB) Operation.......................................................58
3.3.1.1 Reset......................................................................................59