Intel IXC1100, IXP42X 3.5.1.11 Register 10: TLB Lock Down

Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
September 2006 DM
Order Number: 252480-006US 83
Intel XScale® Processor—Intel® IXP42X product line and IXC1100 control plane processors
Tabl e 20 shows the command for locking down entries in the instruction and data
cache. The entry to lock in the instruction cache is specified by the virtual address in
Rd. The data cache locking mechanism follows a different procedure than the
instruction cache. The data cache is placed in lock down mode such that all subsequent
fills to the data cache result in that line being locked in, as controlled by Tabl e 21.
Lock/unlock operations on a disabled cache have an undefined effect.
Read and write access is allowed to the data cache lock register bit[0]. All other
accesses to register 9 should be write-only; reads, as with an MRC, have an undefined
effect.
3.5.1.11 Register 10: TLB Lock Down
Register 10 is used for locking down entries into the instruction TLB, and data TLB.
(The protocol for locking down entries can be found in Chapter 3.0, “Memory
Management Unit”.) Lock/unlock operations on a TLB when the MMU is disabled have
an undefined effect.
This register should be accessed as write-only. Reads from this register, as with an
MRC, have an undefined effect.
Tabl e 22 shows the command for locking down entries in the instruction TLB, and data
TLB. The entry to lock is specified by the virtual address in Rd.
Table 20. Cache Lock-Down Functions
Function opcode_2 CRm Data Instruction
Fetch and Lock I cache line 0b000 0b0001 MVA MCR p15, 0, Rd, c9, c1, 0
Unlock Instruction cache 0b001 0b0001 Ignored MCR p15, 0, Rd, c9, c1, 1
Read data cache lock register 0b000 0b0010 Read lock mode
value MRC p15, 0, Rd, c9, c2, 0
Write data cache lock register 0b000 0b0010 Set/Clear lock
mode MCR p15, 0, Rd, c9, c2, 0
Unlock Data Cache 0b001 0b0010 Ignored MCR p15, 0, Rd, c9, c2, 1
Table 21. Data Cache Lock Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
L
reset value: writeable bits set to 0
Bits Access Description
31:1 Read-unpredictable / Write-as-Zero Reserved
0Read / Write
Data Cache Lock Mode (L)
0 = No locking occurs
1 = Any fill into the data cache while this bit is set gets
locked in
Table 22. TLB Lockdown Functions
Function opcode_2 CRm Data Instruction
Translate and Lock I TLB entry 0b000 0b0100 MVA MCR p15, 0, Rd, c10, c4, 0