Intel IXC1100, IXP42X 19.4 MPHY Polling Routines, 19.5 UTOPIA Level-2 Clocks

Intel® IXP42X product line and IXC1100 control plane processors—UTOPIA Level-2
Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
DM September 2006
546 Order Number: 252480-006US
19.4 MPHY Polling Routines
The UTOPIA Level-2 coprocessor implements a round-robin polling algorithm. The
Receive and Transmit modules use a logical-to-physical address-translation table to
determine the actual physical interface that is to be polled. This feature allows the
designer complete control over the physical address polling sequence.
The multiple-PHY (MPHY) address translation is used by the UTOPIA Level-2 Interface,
on the IXP42X product line and IXC1100 control plane processors, to poll physical
addresses that are not contiguous or do not start at 0.
There are two translation tables implemented. One translation table is used for receive
interface polling and the other translation table is used for transmit interface polling.
Each translation table is implemented as 31 5-bit registers. Each register is addressed
from 0 to 30, corresponding to one of 31 logical addresses.
The five bits of each register are used to designate a physical interface number.
Therefore if a binary value of 00101 is written to address location 0 (logical port 0) of
the transmit translation table, the polling sequence would actually assert a five on the
transmit (UTP_TX_ADDR) address lines of the UTOPIA Level-2 interface during logical
port 0’s turn in the polling algorithm.
For example, make the following assumptions:
• A design requires eight physical interfaces to be connected, which are configured to
respond to addresses 0 through 7.
• The polling order of the physical interfaces is required to be 1, 3, 5, 7, 0, 2, 4, 6 for
both transmit and receive.
To accomplish this polling sequence:
1. The Network Processor Engine core will set the TXADDRRANGE and the
RXADDRRANGE to a hexadecimal value of 0x7.
This will identify that there are eight physical interfaces attached and involved in
the polling sequence.
2. Define the values in both the transmit and receive translation tables as follows:
— Address 0 (logical address 0) = A binary value of 00001
— Address 1 (logical address 1) = A binary value of 00011
— Address 2 (logical address 2) = Aa binary value of 00101
— Address 3 (logical address 3) = Aa binary value of 00111
— Address 4 (logical address 4) = A binary value of 00000
— Address 5 (logical address 5) = A binary value of 00010
— Address 6 (logical address 6) = A binary value of 00100
— Address 7 (logical address 7) = A binary value of 00110
The polling sequence at the physical interface will rotate from logical address 0 through
7. This event will cause the physical address polling values on the UTOPIA Level-2
physical interface to be 1, 3, 5, 7, 0, 2, 4, 6.
19.5 UTOPIA Level-2 Clocks
The UTOPIA Level-2 interface on the IXP42X product line and IXC1100 control plane
processors characterizes the interface for clock speeds of 25 MHz and 33 MHz.