Intel IXC1100, IXP42X 3.1.1 Memory Attributes

Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor

September 2006 DM

Order Number: 252480-006US 45

Intel XScale® Processor—Intel® IXP42X product line and IXC1100 control plane processors

The attributes associated with a particular region of memory are configured in the

memory management page table and control the behavior of accesses to the

instruction cache, data cache, mini-data cache, and the write buffer. These attributes

are ignored when the MMU is disabled.

To allow compatibility with older system software, the new Intel XScale processor

attributes take advantage of encoding space in the descriptors that was formerly

reserved.

3.1.1 Memory Attributes

The selection between address or data coherency is controlled by a software-

programmable P-Attribute bit in the Intel XScale processor’s Memory Management Unit

(MMU) and BYTE_SWAP_EN bit. The BYTE_SWAP_EN bit will be from the Expansion-

Bus Controller Configuration Register 1 Table126, bit 8. When the IXP42X product line

and IXC1100 control plane processors is reset, this bit will reset to 0.

The default endian-conversion method for IXP42X product line and IXC1100 control

plane processors is address coherency. This was selected for backward compatibility

with the IXP425 A0-step device.

The BYTE_SWAP_EN bit is an enable bit that allows data coherency to be performed,

based on the P-Attribute bit.

• When the bit is 0, address coherency is always performed.

• When the bit is 1, the type of coherency performed is dependent on the P-Attribute

bit.

The P-Attribute bit is associated with each 1-Mbyte page. The P-Attribute bit is output

from the Intel XScale processor with any store or load access associated with that

page.

Note: When preparing data for processing by the NPE memory (if byte swapping is necessary

for the application), the P-attribute bit should be used to byte-swap the entire memory

map belonging to the NPE region. For instance, when the Intel XScale processor is

operating in little endian mode, all data arriving from the NPE that is to be read by the

Intel XScale processor should be configured to swap all bytes of data. When writing this

data from the Intel XScale processor to memory (with the intention of the NPE using

this data) all bytes should be swapped using the P-attribute. Using the P-attribute bit to

byte swap all of the NPE memory region will ensure compatible software code porting

to future releases of the Intel XScale processor. Using the P-attribute bit to byte-swap

1-Mbyte regions of the NPE memory may not allow compatible software code porting to

a future Intel XScale microarchitecture.

3.1.1.2.1 Instruction Cache

When examining these bits in a descriptor, the Instruction Cache only utilizes the C bit.

If the C bit is clear, the Instruction Cache considers a code fetch from that memory to

be non-cacheable and will not fill a cache entry. If the C bit is set, then fetches from the

associated memory region will be cached.