Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
September 2006 DM
Order Number: 252480-006US 283
SDRAM Controller—Intel® IXP42X product line and IXC1100 control plane processors
7.2.1 Initializing the SDRAM
Once the Intel XScale processor configures the SDRAM Configuration (SDR_CONFIG)
Register and the SDRAM Refresh (SDR_REFRESH) Register, the following sequence of
commands — using the SDRAM Instruction (SDR_IR) Register — must be performed to
initialize the SDRAM. (This routine can change depending on the SDRAM part that is
connected to the SDRAM interface.)
This routine is included for reference to demonstrate the initialization operation of an
SDRAM:
• The memory controller applies the clock pin (SDM_CKE) during power up and must
stabilize the clock signal within 100 µs after power stabilizes.
• The memory controller holds all the control pins to the memory inactive
(SDM_RAS_N, SDM_CAS_N, SDM_WE_N, SDM_CS_N[1:0]=1) for a minimum of 1
millisecond after supply voltage reaches the desired level.
• SDM_CKE is driven to VCC all the time. The IXP42X product line and IXC1100
control plane processors never de-assert SDM_CKE.
• Software disables the refresh counter by setting SDR_REFRESH to zero.
• Software issues one NOP cycle after the 1milliseconds SDRAM device deselect. A
NOP is accomplished by setting SDR_IR to 011. The memory controller asserts
SDM_CKE with the NOP.
• Software pauses 200 µs after the NOP.
• Software re-enables the refresh counter by setting the SDR_REFRESH to the
required value.
• Software issues a precharge-all command to the SDRAM interface by setting
SDR_IR to 010.
• Software provides eight auto-refresh cycles. An auto-refresh cycle is accomplished
by setting SDR_IR to 100. Software must ensure at least Trc cycles between each
auto-refresh command. Trc (active-to-active command period) is determined by the
SDRAM being used.
• Software issues a mode-register-select command by writing to SDR_IR to program
the SDRAM parameters. Setting SDR_IR to 000 programs the SDRAM Controller for
CAS Latency of two while setting the SDR_IR to 001 programs the memory
controller and SDRAM for CAS Latency of three.
• The SDRAM Controller may issue a row activate command three clocks after the
mode register set command.
Please refer to the chosen SDRAM Memory vendor’s datasheet for SDRAM Initialization
Access to view the operation on the SDRAM signals during the initialization sequence.
In addition to the above features, there is a set of eight registers used by the SDRAM
Controller to manage up to eight open pages. These registers are called the SDRAM
Page (SDR_PG) Registers.
The Intel XScale processor has the ability to read only the status of these registers.
Signals associated with these registers are routed to the Internal Bus Performance
Monitoring Unit (IBPMU). The Internal Bus Performance Monitoring Unit (IBPMU) can
then be used directly to monitor the SDRAM Page Hit/Miss characteristics and Intel
XScale processor code can be optimized to achieve the highest level of performance.
The memory controller may have eight memory pages open simultaneously (one per
leaf). The SDRAM Controller supports devices containing four internal banks. These
internal banks are defined as a leaf to help avoid confusion with a memory bank.