Intel® IXP42X product line and IXC1100 control plane processors—Intel XScale® Processor
Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
DM September 2006
60 Order Number: 252480-006US
A new entry is stored into the BTB when the following conditions are met:
• The branch instruction has executed
• The branch was taken
• The branch is not currently in the BTB
The entry is then marked valid and the history bits are set to WT. If another valid
branch exists at the same entry in the BTB, it will be evicted by the new branch.
Once a branch is stored in the BTB, the history bits are updated upon every execution
of the branch as shown in Figure 11.
The BTB is always disabled with Reset. Software can enable the BTB through a bit in a
coprocessor register (see “Register 1: Control and Auxiliary Control Registers” on
page 77).
Before enabling or disabling the BTB, software must invalidate the BTB (described in
the following section). This action will ensure correct operation in case stale data is in
the BTB. Software should not place any branch instruction between the code that
invalidates the BTB and the code that enables/disables it.
There are four ways the contents of the BTB can be invalidated.
• Reset
• Software can directly invalidate the BTB via a CP15, register 7 function.
Refer to “Register 7: Cache Functions” on page 81.
• The BTB is invalidated when the Process ID Register is written.
• The BTB is invalidated when the instruction cache is invalidated via CP15, register 7
functions.
3.4 Data Cache
The Intel XScale processor data cache enhances performance by reducing the number
of data accesses to and from external memory. There are two data cache structures in
the Intel XScale processor: a 32-Kbyte data cache and a 2-Kbyte mini-data cache. An
eight entry write buffer and a four-entry, fill buffer are also implemented to decouple
the Intel XScale processor instruction execution from external memory accesses, which
increases overall system performance.

3.4.1 Data Cache Overview

The data cache is a 32-Kbyte, 32-way set, associative cache. The 32-Kbyte cache has
32 sets. Each set contains 32 ways. Each way of a set contains 32 bytes (one cache
line) and one valid bit. There also exist two dirty bits for every line, one for the lower
16 bytes and the other one for the upper 16 bytes. When a store hits the cache the
dirty bit associated with it is set. The replacement policy is a round-robin algorithm and
the cache also supports the ability to reconfigure each line as data RAM.
Figure 12, “Data Cache Organization” on page 61 shows the cache organization and
how the data address is used to access the cache.
Cache policies may be adjusted for particular regions of memory by altering page
attribute bits in the MMU descriptor that controls that memory. See “Memory
Attributes” on page 45 for a description of these bits.
The data cache is virtually addressed and virtually tagged. The data cache supports
write-back and write-through caching policies. The data cache always allocates a line in
the cache when a cacheable read miss occurs and will allocate a line into the cache on