Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
September 2006 DM
Order Number: 252480-006US 121
Intel XScale® Processor—Intel® IXP42X product line and IXC1100 control plane processors
2. Load the SELDCSR JTAG instruction into JTAG IR and scan in a value to set the Halt
Mode bit in DCSR and to set the hold_rst signal. For details of the SELDCSR, refer
to “SELDCSR JTAG Register” on page103.
3. After hold_rst is set, de-assert the Reset pin. Internally the processor remains held
in reset.
4. After Reset is de-asserted, wait 2030 TCKs.
5. Load the LDIC JTAG instruction into JTAG IR.
6. Download code into instruction cache in 33-bit packets as described in “LDIC Cache
Functions” on page 118.
7. After code download is complete, clock a minimum of 15 TCKs following the last
update_dr in LDIC mode.
8. Place the SELDCSR JTAG instruction into the JTAG IR and scan in a value to clear
the hold_rst signal. The Halt Mode bit must remain set to prevent the instruction
cache from being invalidated.
9. When hold_rst is cleared, internal reset is de-asserted, and the processor executes
the reset vector at address 0.
An additional issue for debug is setting up the reset vector trap. This must be done
before the internal reset signal is de-asserted. As described in “Vector Trap Bits
(TF,TI,TD,TA,TS,TU,TR)” on page92, the Halt Mode and the Trap Reset bits in the DCSR
must be set prior to de-asserting reset in order to trap the reset vector. There are two
possibilities for setting up the reset vector trap:
• The reset vector trap can be set up before the instruction cache is loaded by
scanning in a DCSR value that sets the Trap Reset bit in addition to the Halt Mode
bit and the hold_rst signal; OR
• The reset vector trap can be set up after the instruction cache is loaded. In this
case, the DCSR should be set up to do a reset vector trap, with the Halt Mode bit
and the hold_rst signal remaining set.
In either case, when the debugger clears the hold_rst bit to de-assert internal reset,
the debugger must set the Halt Mode and Trap Reset bits in the DCSR.
3.6.14.4.2 Loading IC During a Warm Reset for Debug
Loading the instruction cache during a warm reset may be a slightly different situation
than during a cold reset. For a warm reset, the main issue is whether the instruction
cache gets invalidated by the processor reset or not. There are several possible
scenarios:
• While reset is asserted, TRST is also asserted.
In this case the instruction cache is invalidated, so the actions taken to download
code are identical to those described in “Loading IC During Cold Reset for Debug”
on page 120
• When reset is asserted, TRST is not asserted, but the processor is not in Halt Mode.
In this case, the instruction cache is also invalidated, so the actions are the same
as described in “Loading IC During Cold Reset for Debug” on page 120, after the
LDIC instruction is loaded into the JTAG IR.
• When reset is asserted, TRST is not asserted, and the processor is in Halt Mode.
In this last scenario, the mini instruction cache does not get invalidated by reset,
since the processor is in Halt Mode. This scenario is described in more detail in this
section.
In the last scenario described above is shown in Figure 28.