Main
Page
Contents
Page
Page
Page
Page
Page
Page
Page
Page
Page
Page
Page
Page
Page
Figures
Page
Tables
Page
Page
Page
Revision History
Page
Page
1.0 Introduction
1.1 About This Document
1.1.1 How to Read This Document
1.2 Other Relevant Documents
1.3 Terminology and Conventions
1.3.2 Acronyms and Terminology
Table 1. Acronyms and Terminology
Table 1. Acronyms and Terminology (Continued)
Page
2.0 Overview of Product Line
Order Number: 252480-006US 31
Overview of Product LineIntel IXP42X product line and IXC1100 control plane processors
Figure 1. Intel IXP425 Network Processor Block Diagram
B1563-04
Ethernet NPE B
Ethernet NPE A
WAN/Voice NPE
Figure 2. Intel IXP423 Network Processor Block Diagram
B4285-02
Ethernet NPE B
Intel XScale
Ethernet NPE A
Figure 3. Intel IXP422 Network Processor Block Diagram
B1566-04
Ethernet NPE A
Intel XScale
North AHB Arbiter
Figure 4. Intel IXP421 Network Processor Block Diagram
B1565-04
Ethernet NPE A
Intel XScale
WAN/Voice NPE
2.1 Intel XScale Microarchitecture Processor
Page
2.1.1.3 Memory Management
2.1.1.4 Instruction Cache
2.1.1.5 Branch Target Buffer
2.1.1.6 Data Cache
2.1.1.7 Intel XScale Processor Performance Monitoring
2.2 Network Processor Engines (NPE)
2.3 Internal Bus
2.4 MII Interfaces
2.5 AHB Queue Manager
2.6 UTOPIA 2
2.7 USB v1.1
2.8 PCI
2.9 Memory Controller
2.10 Expansion Bus
2.11 High-Speed Serial Interfaces
2.12 Universal Asynchronous Receiver Transceiver
2.13 GPIO
2.14 Interrupt Controller
2.15 Timers
2.16 JTAG
3.0 Intel XScale Processor
3.1 Memory Management Unit
3.1.1 Memory Attributes
3.1.1.1 Page (P) Attribute Bit
3.1.1.2 Cacheable (C), Bufferable (B), and eXtension (X) Bits
Page
3.1.2 Interaction of the MMU, Instruction Cache, and Data Cache
3.1.3 MMU Control
3.1.3.1 Invalidate (Flush) Operation
3.1.3.2 Enabling/Disabling
3.1.3.3 Locking Entries
Page
3.1.3.4 Round-Robin Replacement Algorithm
3.2 Instruction Cache
3.2.1 Operation When Instruction Cache is Enabled
3.2.1.1 Instruction-Cache Miss
Example: 32K byte cache
3.2.1.2 Instruction-Cache Line-Replacement Algorithm
3.2.1.3 Instruction-Cache Coherence
Page
Page
3.3 Branch Target Buffer
3.3.1 Branch Target Buffer (BTB) Operation
Page
3.4 Data Cache
3.4.1 Data Cache Overview
Example: 32-Kbyte cache
Example: 2K byte cache
3.4.2 Cacheability
Page
Page
Page
Example 9. Global Clean Operation
3.4.3 Reconfiguring the Data Cache as Data RAM
Example 10. Locking Data into Data Cache
Page
Example 11. Creating Data RAM
...
... ......
3.5 Configuration
Page
3.5.1 CP15 Registers
Table 8. LDC/STC Format when Accessing CP14
Table 9. CP15 Registers (Sheet 1 of 2)
3.5.1.1 Register 0: ID and Cache Type Registers
Table 9. CP15 Registers (Sheet 2 of 2)
Table 10. ID Register
3.5.1.2 Register 1: Control and Auxiliary Control Registers
Table 12. ARM* Control Register (Sheet 2 of 2)
3.5.1.3 Register 2: Translation Table Base Register
Table 13. Auxiliary Control Register
Table 14. Translation Table Base Register
3.5.1.4 Register 3: Domain Access Control Register
3.5.1.5 Register 4: Reserved
3.5.1.6 Register 5: Fault Status Register
3.5.1.7 Register 6: Fault Address Register
3.5.1.8 Register 7: Cache Functions
3.5.1.9 Register 8: TLB Operations
3.5.1.10 Register 9: Cache Lock Down
3.5.1.11 Register 10: TLB Lock Down
3.5.1.12 Register 11-12: Reserved
3.5.1.13 Register 13: Process ID
3.5.1.14 The PID Register Affect On Addresses
3.5.1.15 Register 14: Breakpoint Registers
3.5.1.16 Register 15: Coprocessor Access Register
Example 12. Disallowing access to CP0
3.5.2 CP14 Registers
Tabl e 27 lists the CP14 registers implemented in the Intel XScale processor.
All other registers are reserved in CP14. Reading and writing them yields unpredictable results.
Table 26. Coprocessor Access Register
Table 27. CP14 Registers
3.5.2.1 Performance Monitoring Registers
3.5.2.2 Clock and Power Management Registers
3.5.2.3 Software Debug Registers
3.6 Software Debug
3.6.1 Definitions
3.6.2 Debug Registers
3.6.3 Debug Modes
3.6.3.1 Halt Mode
3.6.3.2 Monitor Mode
3.6.4 Debug Control and Status Register (DCSR)
3.6.4.1 Global Enable Bit (GE)
3.6.4.2 Halt Mode Bit (H)
3.6.4.3 Vector Trap Bits (TF,TI,TD,TA,TS,TU,TR)
3.6.4.4 Sticky Abort Bit (SA)
3.6.4.5 Method of Entry Bits (MOE)
3.6.5 Debug Exceptions
3.6.5.1 Halt Mode
3.6.5.2 Monitor Mode
3.6.6 HW Breakpoint Resources
3.6.6.1 Instruction Breakpoints
3.6.6.2 Data Breakpoints
Page
3.6.7 Software Breakpoints
3.6.8 Transmit/Receive Control Register
(TXRXCTRL)
3.6.8.1 RX Register Ready Bit (RR)
3.6.8.2 Overflow Flag (OV)
3.6.8.3 Download Flag (D)
3.6.8.4 TX Register Ready Bit (TR)
3.6.8.5 Conditional Execution Using TXRXCTRL
3.6.9 Transmit Register
(TX)
3.6.10 Receive Register
(RX)
3.6.11 Debug JTAG Access
3.6.11.1 SELDCSR JTAG Command
Page
TDO
DBG_SR
DBG_REG
TDI
Page
Page
Core CLK
DBG_REG[34]
TXRXCTRL[31]
Clear DBG_REG[34] RX write enable set TXRXCTRL[31] set overflow flag (TXRXCTRL[30])
TDO
DBG_SR
DBG_REG
TDI
3.6.11.7 Debug JTAG Data Register Reset Values
3.6.12 Trace Buffer
3.6.12.1 Trace Buffer CP Registers
Page
3.6.13 Trace Buffer Entries
3.6.13.1 Message Byte
Page
Page
Page
Page
3.6.14 Downloading Code in ICache
3.6.14.1 LDIC JTAG Command
Page
3.6.14.3 LDIC Cache Functions
3.6.14.4 Loading IC During Reset
Page
Page
Page
3.6.14.5 Dynamically Loading IC After Reset
Debugger Actions
Debug Handler Actions
Page
Table 51. Debug-Handler Code to Implement Synchronization During Dynamic Code Download
3.6.14.6 Mini-Instruction Cache Overview
3.6.15 Halt Mode Software Protocol
3.6.15.1 Starting a Debug Session
Page
3.6.15.2 Implementing a Debug Handler
Page
Page
3.6.15.3 Ending a Debug Session
3.6.16 Software Debug Notes and Errata
3.7 Performance Monitoring
3.7.1 Overview
3.7.2 Register Description
3.7.2.1 Clock Counter (CCNT)
3.7.2.2 Performance Count Registers
(PMN0 - PMN3)
3.7.2.3 Performance Monitor Control Register
(PMNC)
Table 55. Performance Monitor Count Register (PMN0 - PMN3)
Table 56. Performance Monitor Control Register
3.7.2.4 Interrupt Enable Register
(INTEN)
3.7.2.5 Overflow Flag Status Register
(FLAG)
Table 57. Interrupt Enable Register
3.7.2.6 Event Select Register
(EVTSEL)
Table 58. Overflow Flag Status Register
3.7.3 Managing the Performance Monitor
3.7.4 Performance Monitoring Events
3.7.4.1 Instruction Cache Efficiency Mode
3.7.4.2 Data Cache Efficiency Mode
3.7.4.3 Instruction Fetch Latency Mode
3.7.4.4 Data/Bus Request Buffer Full Mode
3.7.4.5 Stall/Write-Back Statistics
3.7.4.6 Instruction TLB Efficiency Mode
3.7.4.7 Data TLB Efficiency Mode
3.7.5 Multiple Performance Monitoring Run Statistics
3.7.6 Examples
Counter overflow can be dealt with in the IRQ interrupt service routine as shown below:
As an example, assume the following values in CCNT, PMN0, PMN1 and PMNC:
Example 14. Configuring the Performance Monitor
Example 15. Interrupt Handling
3.8 Programming Model
3.8.1 ARM* Architecture Compatibility
3.8.2 ARM* Architecture Implementation Options
3.8.2.1 Big Endian versus Little Endian
3.8.2.2 26-Bit Architecture
3.8.2.3 Thumb
3.8.2.4 ARM* DSP-Enhanced Instruction Set
3.8.2.5 Base Register Update
3.8.3 Extensions to ARM* Architecture
3.8.3.1 DSP Coprocessor 0 (CP0)
Page
Page
Page
Page
Page
3.8.3.2 New Page Attributes
3.8.3.3 Additions to CP15 Functionality
3.8.3.4 Event Architecture
Page
Page
Page
Page
3.9 Performance Considerations
3.9.1 Interrupt Latency
3.9.2 Branch Prediction
3.9.3 Addressing Modes
3.9.4 Instruction Latencies
3.9.4.1 Performance Terms
Page
3.9.4.2 Branch Instruction Timings
3.9.4.3 Data Processing Instruction Timings
Table 77. Latency Example
Table 78. Branch Instruction Timings (Those Predicted by the BTB)
Table 79. Branch Instruction Timings (Those not Predicted by the BTB)
3.9.4.4 Multiply Instruction Timings
Table 81. Multiply Instruction Timings (Sheet 1 of 2)
Table 80. Data Processing Instruction Timings (Sheet 2 of 2)
Table 81. Multiply Instruction Timings (Sheet 2 of 2)
3.9.4.5 Saturated Arithmetic Instructions
3.9.4.6 Status Register Access Instructions
3.9.4.7 Load/Store Instructions
Table 82. Multiply Implicit Accumulate Instruction Timings
Table 83. Implicit Accumulator Access Instruction Timings
3.9.4.8 Semaphore Instructions
3.9.4.9 Coprocessor Instructions
Table 87. Load and Store Multiple Instruction Timings
Table 88. Semaphore Instruction Timings
Table 89. CP15 Register Access Instruction Timings
3.10 Optimization Guide
3.10.1 Introduction
3.10.1.1 About This Section
3.10.2 Processors Pipeline
3.10.2.1 General Pipeline Characteristics
F1 F2 ID RF X1 X2 XWB M1 M2 Mx
D1 D2
3.10.2.2 Instruction Flow Through the Pipeline
3.10.2.3 Main Execution Pipeline
3.10.2.4 Memory Pipeline
3.10.2.5 Multiply/Multiply Accumulate (MAC) Pipeline
3.10.3 Basic Optimizations
3.10.3.1 Conditional Instructions
Page
Page
Page
Page
3.10.3.2 Bit Field Manipulation
3.10.3.3 Optimizing the Use of Immediate Values
3.10.3.4 Optimizing Integer Multiply and Divide
3.10.3.5 Effective Use of Addressing Modes
3.10.4 Cache and Prefetch Optimizations
3.10.4.1 Instruction Cache
3.10.4.2 Data and Mini Cache
Page
Page
3.10.4.3 Cache Considerations
3.10.4.4 Prefetch Considerations
Page
Page
Page
Page
Page
3.10.5 Instruction Scheduling
3.10.5.1 Scheduling Loads
Page
Page
Page
3.10.5.2 Scheduling Data Processing Instructions
3.10.5.3 Scheduling Multiply Instructions
3.10.5.4 Scheduling SWP and SWPB Instructions
3.10.5.5 Scheduling the MRA and MAR Instructions (MRRC/MCRR)
3.10.5.6 Scheduling the MIA and MIAPH Instructions
3.10.5.7 Scheduling MRS and MSR Instructions
3.10.5.8 Scheduling CP15 Coprocessor Instructions
3.10.6 Optimizing C Libraries
3.10.7 Optimizations for Size
3.10.7.1 Space/Performance Trade Off
Page
Page
4.0 Network Processor Engines (NPE)
Page
5.0 Internal Bus
5.1 Internal Bus Arbiters
5.1.1 Priority Mechanism
5.2 Memory Map
Table 96. Memory Map
Page
6.0 PCI Controller
Figure 30. Processors PCI Bus Configured as a Host
Figure 31. Processors PCI Bus Configured as an Option
Page
Page
Page
6.1 PCI Controller Configured as Host
Page
Page
6.1.1 Example: Generating a PCI Configuration Write and Read
Page
6.2 PCI Controller Configured as Option
6.3 Initializing PCI Controller Configuration and Status Registers for Data Transactions
Page
Page
6.3.2 Example: PCI Memory Base Address Register and South-AHB Translation
6.4 Initializing the PCI Controller Configuration Registers
Page
Page
6.5 PCI Controller South AHB Transactions
Table 101. PCI Configuration Space
Table 102. Command Type for PCI Controller Configuration and Status Register Accesses
Table 100. PCI Byte Enables Using CRP Access Method
6.6 PCI Controller Functioning as Bus Initiator
6.6.1 PCI Byte Enables
6.6.2 Initiated Type-0 Read Transaction
6.6.3 Initiated Type-0 Write Transaction
6.6.4 Initiated Type-1 Read Transaction
6.6.5 Initiated Type-1 Write Transaction
6.6.6 Initiated Memory Read Transaction
6.6.7 Initiated Memory Write Transaction
6.6.8 Initiated I/O Read Transaction
6.6.9 Initiated I/O Write Transaction
6.6.10 Initiated Burst Memory Read Transaction
6.6.11 Initiated Burst Memory Write Transaction
6.7 PCI Controller Functioning as Bus Target
6.8 PCI Controller DMA Controller
Page
Page
Page
6.8.1 AHB to PCI DMA Channel Operation
6.8.2 PCI to AHB DMA Channel Operation
6.9 PCI Controller Door Bell Register
6.10 PCI Controller Interrupts
6.10.1 PCI Interrupt Generation
6.10.2 Internal Interrupt Generation
6.11 PCI Controller Endian Control
Page
Page
Page
Page
Page
Page
6.12 PCI Controller Clock and Reset Generation
6.13 PCI RCOMP Circuitry
6.14 Register Descriptions
6.14.1 PCI Configuration Registers
6.14.1.1 Device ID/Vendor ID Register (PCI_DIDVID)
6.14.1.2 Status Register/Control Register (PCI_SRCR)
Table 103. PCI Configuration Register Map (Sheet 2 of 2)
Page
6.14.1.3 Class Code/Revision ID Register (PCI_CCRID)
6.14.1.4 BIST/Header Type/Latency Timer/Cache Line Register (PCI_BHLC)
6.14.1.5 Base Address 0 Register (PCI_BAR0)
6.14.1.6 Base Address 1 Register (PCI_BAR1)
6.14.1.7 Base Address 2 Register (PCI_BAR2)
6.14.1.8 Base Address 3 Register (PCI_BAR3)
6.14.1.9 Base Address 4 Register (PCI_BAR4)
6.14.1.10 Base Address 5 Register (PCI_BAR5)
6.14.1.11 Subsystem ID/Subsystem Vendor ID Register (PCI_SIDSVID)
6.14.1.12 Max_Lat, Min_Gnt, Interrupt Pin, and Interrupt Line Register (PCI_LATINT)
6.14.1.13 Retry Timeout/TRDY Timeout Register (PCI_RTOTTO)
6.14.2 PCI Controller Configuration and Status Registers
6.14.2.1 PCI Controller Non-pre-fetch Address Register (PCI_NP_AD)
6.14.2.2 PCI Controller Non-pre-fetch Command/Byte Enables Register (PCI_NP_CBE)
6.14.2.3 PCI Controller Non-Pre-fetch Write Data Register (PCI_NP_WDATA)
6.14.2.4 PCI Controller Non-Pre-fetch Read Data Register (PCI_NP_RDATA)
6.14.2.5 PCI Controller Configuration Port Address/Command/ Byte Enables Register (PCI_CRP_AD_CBE)
6.14.2.6 PCI Controller Configuration Port Write Data Register (PCI_CRP_WDATA)
6.14.2.7 PCI Controller Configuration Port Read Data Register (PCI_CRP_RDATA)
6.14.2.8 PCI Controller Control and Status Register (PCI_CSR)
6.14.2.9 PCI Controller Interrupt Status Register (PCI_ISR)
6.14.2.10 PCI Controller Interrupt Enable Register (PCI_INTEN)
6.14.2.11 DMA Control Register (PCI_DMACTRL)
6.14.2.12 AHB Memory Base Address Register (PCI_AHBMEMBASE)
6.14.2.13 AHB I/O Base Address Register (PCI_AHBIOBASE)
6.14.2.14 PCI Memory Base Address Register (PCI_PCIMEMBASE)
6.14.2.15 AHB Doorbell Register (PCI_AHBDOORBELL)
6.14.2.16 PCI Doorbell Register (PCI_PCIDOORBELL)
6.14.2.17 AHB to PCI DMA AHB Address Register 0 (PCI_ATPDMA0_AHBADDR)
6.14.2.18 AHB to PCI DMA PCI Address Register 0 (PCI_ATPDMA0_PCIADDR)
6.14.2.19 AHB to PCI DMA Length Register 0 (PCI_ATPDMA0_LENGTH)
6.14.2.20 AHB to PCI DMA AHB Address Register 1 (PCI_ATPDMA1_AHBADDR)
6.14.2.21 AHB to PCI DMA PCI Address Register 1 (PCI_ATPDMA1_PCIADDR)
6.14.2.22 AHB to PCI DMA Length Register 1 (PCI_ATPDMA1_LENGTH)
6.14.2.23 PCI to AHB DMA AHB Address Register 0 (PCI_PTADMA0_AHBADDR)
6.14.2.24 PCI to AHB DMA PCI Address Register 0 (PCI_PTADMA0_PCIADDR)
6.14.2.25 PCI to AHB DMA Length Register 0 (PCI_PTADMA0_LENGTH)
6.14.2.26 PCI to AHB DMA AHB Address Register 1 (PCI_PTADMA1_AHBADDR)
6.14.2.27 PCI to AHB DMA PCI Address Register 1 (PCI_PTADMA1_PCIADDR)
6.14.2.28 PCI to AHB DMA Length Register 1 (PCI_PTADMA1_LENGTH)
Page
Page
7.0 SDRAM Controller
Order Number: 252480-006US 277
SDRAM ControllerIntel IXP42X product line and IXC1100 control plane processors
Figure 53. 8-, 16-, 32-, 64- or 128-Mbyte One-Bank SDRAM Interface Configuration
B4963-01
Intel IXP42X Product Line / Intel IXC1100 Control Plane Processor
Intel IXP42X product line and IXC1100 control plane processorsSDRAM Controller
278 Order Number: 252480-006US
Figure 54. 64-, 128- or 256-Mbyte Two-Bank SDRAM Interface Configuration
Intel
B4964-01
IXP42X Product Line / Intel
IXC1100 Control Plane Processor
7.1 SDRAM Memory Space
7.2 Initializing the SDRAM Controller
Page
Page
Page
7.2.1 Initializing the SDRAM
Page
7.3 SDRAM Memory Accesses
7.3.1 Read Transfer
7.3.1.1 Read Cycle Timing (CAS Latency of Two Cycles)
Intel IXP42X product line and IXC1100 control plane processorsSDRAM Controller
286 Order Number: 252480-006US
7.3.2 Write Transfer
7.3.2.1 Write Transfer
Figure 56. SDRAM Shared South AHB and North AHB Access
SDRAM CYCLE READ CAS LATENCY = 2 Transaction on AHB1 and AHB0
7.4 Register Description
7.4.1 Configuration Register
7.4.2 Refresh Register
7.4.3 Instruction Register
Table 114. SDRAM Configuration Options
Table 115. SDRAM Burst Definitions
Table 115. SDRAM Burst Definitions
Table 116. SDRAM Commands
Page
8.0 Expansion Bus Controller
8.1 Expansion Bus Address Space
8.2 Chip Select Address Allocation
8.3 Address and Data Byte Steering
SIZE = 2
cs_n[x]
Table 118. Expansion Bus Address and Data Byte Steering
8.4 Expansion Bus Connections
8.5 Expansion Bus Interface Configuration
Page
Page
8.6 Using I/O Wait
Page
8.7 Special Design Knowledge for Using HPI mode
....
Page
8.8 Expansion Bus Interface Access Timing Diagrams
8.8.1 Intel Multiplexed-Mode Write Access
Figure 63. Expansion-Bus Write (Intel Multiplexed Mode)
8.8.2 Intel Multiplexed-Mode Read Access
Figure 64. Expansion-Bus Read (Intel Multiplexed Mode)
8.8.3 Intel Simplex-Mode Write Access
Figure 65. Expansion-Bus Write (Intel Simplex Write Mode)
Valid Address
T1 T2 T3 T4 T5
8.8.4 Intel Simplex-Mode Read Access
Figure 66. Expansion-Bus Read (Intel Simplex Mode)
Valid Data
Valid Address
T1 T2 T3 T4 T5
8.8.5 Motorola* Multiplexed-Mode Write Access
Figure 67. Expansion-Bus Write (Motorola* Multiplexed Mode)
8.8.6 Motorola* Multiplexed-Mode Read Access
Figure 68. Expansion-Bus Read (Motorola* Multiplexed Mode)
8.8.7 Motorola* Simplex-Mode Write Access
Figure 69. Expansion-Bus Write (Motorola* Simplex Mode)
8.8.8 Motorola* Simplex-Mode Read Access
Figure 70. Expansion-Bus Read (Motorola* Simplex Mode)
8.8.9 TI* HPI-8 Write Access
Figure 71. Expansion-Bus Write (TI* HPI-8 Mode)
Valid Address
T1 T2 T3 T4 T5
HPI-8 Mode Write
8.8.10 TI* HPI-8 Read Access
Figure 72. Expansion-Bus Read (TI* HPI-8 Mode)
Accesses
Valid Address
T1 T2 T3 T4 T5
8.8.11 TI* HPI-16, Multiplexed-Mode Write Access
Figure 73. Expansion-Bus Write (TI* HPI-16 Multiplexed Mode)
8.8.12 TI* HPI-16, Multiplexed-Mode Read Access
Figure 74. Expansion-Bus Read (TI* HPI-16 Multiplexed Mode)
8.8.13 TI* HPI-16 Simplex-Mode Write Access
Figure 75. Expansion-Bus Write (TI* HPI-16 Simplex Mode)
8.8.14 TI* HPI-16 Simplex-Mode Read Access
Figure 76. Expansion-Bus Read (TI* HPI-16 Simplex Mode)
8.9 Register Descriptions
8.9.1 Timing and Control Registers for Chip Select 0
8.9.2 Timing and Control Registers for Chip Select 1
Table 122. Expansion Bus Register Overview
8.9.3 Timing and Control Registers for Chip Select 2
8.9.4 Timing and Control Registers for Chip Select 3
8.9.5 Timing and Control Registers for Chip Select 4
8.9.6 Timing and Control Registers for Chip Select 5
8.9.7 Timing and Control Registers for Chip Select 6
8.9.8 Timing and Control Registers for Chip Select 7
8.9.9 Configuration Register 0
Table 123. Bit Level Definition for each of the Timing and Control Registers
Table 124. Configuration Register 0 Description
8.9.9.1 User-Configurable Field
8.9.10 Configuration Register 1
BYTE_SWAP_EN
Table 126. Expansion Bus Configuration Register 1-Bit Definition
8.10 Expansion Bus Controller Performance
Tabl e 127 shows simulated expansion bus throughput.
Table 127. Simulated Expansion Bus Performance
Page
9.0 AHB/APB Bridge
Order Number: 252480-006US 329
AHB/APB BridgeIntel IXP42X product line and IXC1100 control plane processors
Figure 77. APB Interface
Table 128. Address Map for the APB
Page
10.0 Universal Asynchronous Receiver Transceiver (UART)
10.1 High Speed UART
Start
LSB MSB
UART TXD or RXD
Bit Definition
Figure 79. UART Block Diagram
10.2 Configuring the UART
10.2.1 Setting the Baud Rate
10.2.2 Setting Data Bits/Stop Bits/Parity
Page
10.2.3 Using the Modem Control Signals
10.2.4 UART Interrupts
Page
Page
10.3 Transmitting and Receiving UART Data
10110
Page
10.4 Register Descriptions
10.4.1 Receive Buffer Register
10.4.2 Transmit Holding Register
10.4.3 Divisor Latch Low Register
10.4.4 Divisor Latch High Register
10.4.5 Interrupt Enable Register
10.4.6 Interrupt Identification Register
Page
10.4.7 FIFO Control Register
Table 135. UART IDD Bit Mapping
10.4.8 Line Control Register
Page
10.4.9 Modem Control Register
0 = Normal UART operation 1 = Test mode UART operation
10.4.10 Line Status Register
10.4.11 Modem Status Register
10.4.12 Scratch-Pad Register
10.4.13 Infrared Selection Register
10.5 Console UART
10.5.1 Register Description
Table 136. Console UART Registers Overview
10.5.1.1 Receive Buffer Register
10.5.1.2 Transmit Holding Register
Table 136. Console U ART Registers Overview
10.5.1.3 Divisor Latch Low Register
10.5.1.4 Divisor Latch High Register
10.5.1.5 Interrupt Enable Register
The DLAB bit in the Line Control Register must be set to logic 0 to access this register.
10.5.1.6 Interrupt Identification Register
Table 137. Priority Levels of Interrupt Identification Register
10.5.1.7 FIFO Control Register
Table 138. UART Interrupt Identification Bit Level Definition
10.5.1.8 Line Control Register
Page
10.5.1.9 Modem Control Register
10.5.1.10 Line Status Register
10.5.1.11 Modem Status Register
10.5.1.12 Scratch-Pad Register
10.5.1.13 Infrared Selection Register
Page
Page
11.0 Internal Bus Performance Monitoring Unit (IBPMU)
11.1 Initializing the IBPMU
11.2 Using the IBPMU
Page
11.2.1 Monitored Events South AHB and North AHB
Table 142. North and South Modes Event Descriptions (Sheet 1 of 2)
11.2.2 Monitored SDRAM Events
11.2.3 Cycle Count
Table 142. North and South Modes Event Descriptions (Sheet 2 of 2)
11.3 Register Descriptions
11.3.1 Event Select Register
Page
Table 144. Possible Event Settings
11.3.2 PMU Status Register (PSR)
11.3.3 Programmable Event Counters (PEC1)
11.3.4 Programmable Event Counters (PEC2)
11.3.5 Programmable Event Counters (PEC3)
11.3.6 Programmable Event Counters (PEC4)
11.3.7 Programmable Event Counters (PEC5)
11.3.8 Programmable Event Counters (PEC6)
11.3.9 Programmable Event Counters (PEC7)
11.3.10 Previous Master/Slave Register (PSMR)
Page
12.0 General Purpose Input/Output (GPIO)
12.1 Using GPIO as Inputs/Outputs
12.2 Using GPIO as Interrupt Inputs
Page
12.3 Using GPIO 14 and GPIO 15 as Clocks
Table 146. GPIO Clock Frequency Select
Table 147. GPIO Duty Cycle Select (Sheet 1 of 2)
12.4 Register Description
12.4.1 GPIO Output Register (GPOUTR)
Table 147. GPIO Duty Cycle Select (Sheet 2 of 2)
Table 148. GPIO Registers Overview
12.4.2 GPIO Output Enable Register (GPOER)
12.4.3 GPIO Input Register (GPINR)
This is a read-only register. This register contains the level of the I/O pin, either a 1 or a 0.
12.4.4 GPIO Interrupt Status Register (GPISR)
12.4.5 GP Interrupt Type Register 1 (GPIT1R)
12.4.6 GPIO Interrupt Type Register 2 (GPIT2R)
12.4.7 GPIO Clock Register (GPCLKR)
Page
Page
13.0 Interrupt Controller
13.1 Interrupt Priority
13.2 Assigning FIQ or IRQ Interrupts
13.3 Enabling and Disabling Interrupts
13.4 Reading Interrupt Status
13.5 Interrupt Controller Register Description
13.5.1 Interrupt Status Register
Table 149. Interrupt Controller Registers
Page
13.5.2 Interrupt-Enable Register
13.5.3 Interrupt Select Register
13.5.5 FIQ Status Register
13.5.4 IRQ Status Register
13.5.6 Interrupt Priority Register
13.5.7 IRQ Highest-Priority Register
13.5.8 FIQ Highest-Priority Register
Page
14.0 Timers
14.1 Watch-Dog Timer
14.2 Time-Stamp Timer
14.3 General-Purpose Timers
Page
14.4 Timer Register Definition
14.4.1 Time-Stamp Timer
14.4.2 General-Purpose Timer 0
Table 150. Timer Registers
14.4.3 General-Purpose Timer 0 Reload
14.4.4 General-Purpose Timer 1
14.4.5 General-Purpose Timer 1 Reload
14.4.6 Watch-Dog Timer
14.4.7 Watch-Dog Enable Register
14.4.8 Watch-Dog Key Register
14.4.9 Timer Status
15.0 Ethernet MAC A
15.1 Ethernet Coprocessor
Figure 80. Multiple Ethernet PHYS Connected to Processor
Intel IXP42X Product Line / IXC1100 Control Plane Processor
Figure 81. Ethernet Coprocessor Interface
Interface Logic
15.1.1 Ethernet Coprocessor APB Interface
15.1.2 Ethernet Coprocessor NPE Interface
15.1.3 Ethernet Coprocessor MDIO Interface
Page
15.1.4 Transmitting Ethernet Frames with MII Interfaces
Figure 82. MDIO Write
Figure 83. MDIO Read
MDC MDIO
MDC MDIO
Page
Page
15.1.5 Receiving Ethernet Frames with MII Interfaces
Page
15.1.6 General Ethernet Coprocessor Configuration
Page
15.2 Register Descriptions
15.2.1 Transmit Control 1
15.2.2 Transmit Control 2
15.2.3 Receive Control 1
15.2.4 Receive Control 2
15.2.5 Random Seed
15.2.6 Threshold For Partially Empty
15.2.7 Threshold For Partially Full
15.2.8 Buffer Size For Transmit
15.2.9 Transmit Deferral Parameters
15.2.10 Receive Deferral Parameters
15.2.11 Transmit Two Part Deferral Parameters 1
15.2.12 Transmit Two Part Deferral Parameters 2
15.2.13 Slot Time
15.2.14 MDIO Commands Registers
15.2.16 MDIO Command 2
15.2.15 MDIO Command 1
15.2.17 MDIO Command 3
15.2.18 MDIO Command 4
15.2.19 MDIO Status Registers
15.2.20 MDIO Status 1
15.2.21 MDIO Status 2
15.2.23 MDIO Status 4
15.2.22 MDIO Status 3
15.2.24 Address Mask Registers
15.2.25 Address Mask 1
15.2.26 Address Mask 2
15.2.27 Address Mask 3
15.2.29 Address Mask 5
15.2.28 Address Mask 4
15.2.30 Address Mask 6
15.2.31 Address Registers
15.2.32 Address 1
15.2.33 Address 2
15.2.35 Address 4
15.2.34 Address 3
15.2.36 Address 5
15.2.37 Address 6
15.2.38 Threshold for Internal Clock
15.2.39 Unicast Address Registers
15.2.40 Unicast Address 1
15.2.41 Unicast Address 2
15.2.43 Unicast Address 4
15.2.42 Unicast Address 3
15.2.44 Unicast Address 5
15.2.45 Unicast Address 6
15.2.46 Core Control
Page
16.0 Ethernet MAC B
Table 153. Ethernet MAC B Registers (Sheet 1 of 2)
Table 153. Ethernet MAC B Registers (Sheet 2 of 2)
17.0 High-Speed Serial Interfaces
17.1 High-Speed Serial Interface Receive Operation
17.2 High-Speed Serial Interface Transmit Operation
17.3 Configuration of the High-Speed Serial Interface
Page
Page
17.4 Obtaining High-Speed, Serial Synchronization
17.5 HSS Registers and Clock Configuration
17.5.1 HSS Clock and Jitter
17.5.2 Overview of HSS Clock Configuration
Table 156. HSS Tx/Rx Clock Output Frequencies and PPM Error
Table 155. HSS Tx/Rx Clock Output
Table 157. HSS Tx/Rx Clock Output Frequencies And Their Associated Jitter Characterization
Table 158. HSS Frame Output Characterization
17.6 HSS Supported Framing Protocols
hss_rx_data
hss_rx_clock hss_rx_frame FBit data1 data 192data 191 FBitdata2 data1
17.6.2 E1
hss_tx_data
hss_tx_cl ock hss_tx_fr ame data 1 data 2 data 3 data 256data 255 data 1 data 2
17.6.3 MVIP
hss_rx_data
hss_rx_clock hss_rx_frame data1 data3 data2data1data256data2 data255
17.6.3.1 MVIP using 2.048Mbps Backplane
Page
17.6.3.2 MVIP Using 4.096-Mbps Backplane
17.6.3.3 MVIP Using 8.192-Mbps Backplane
Page
Page
Page
18.0 Universal Serial Bus (USB) v1.1 Device Controller
18.1 USB Overview
18.2 Device Configuration
18.3 USB Operation
18.3.1 Signalling Levels
18.3.2 Bit Encoding
18.3.3 Field Formats
Page
18.3.4 Packet Formats
18.3.4.1 Token Packet Type
18.3.4.2 Start-of-Frame Packet Type
18.3.4.3 Data Packet Type
18.3.4.4 Handshake Packet Type
18.3.5 Transaction Formats
18.3.5.1 Bulk Transaction Type
18.3.5.2 Isochronous Transaction Type
18.3.5.3 Control Transaction Type
18.3.5.4 Interrupt Transaction Type
18.3.6 UDC Device Requests
18.3.7 UDC Configuration
18.4 UDC Hardware Connections
18.4.1 Self-Powered Device
18.4.2 Bus-Powered Devices
18.5 Register Descriptions
Page
18.5.1 UDC Control Register (UDCCR)
18.5.1.1 UDC Enable
18.5.1.2 UDC Active
18.5.1.3 UDC Resume (RSM)
18.5.1.4 Resume Interrupt Request (RESIR)
18.5.1.5 Suspend Interrupt Request (SUSIR)
18.5.1.6 Suspend/Resume Interrupt Mask (SRM)
18.5.1.7 Reset Interrupt Request (RSTIR)
18.5.1.8 Reset Interrupt Mask (REM)
18.5.2 UDC Endpoint 0 Control/Status Register (UDCCS0)
18.5.2.1 OUT Packet Ready (OPR)
18.5.2.2 IN Packet Ready (IPR)
18.5.2.3 Flush Tx FIFO (FTF)
18.5.2.4 Device Remote Wake-Up Feature (DRWF)
18.5.2.5 Sent Stall (SST)
18.5.2.6 Force Stall (FST)
18.5.2.7 Receive FIFO Not Empty (RNE)
18.5.3 UDC Endpoint 1 Control/Status Register (UDCCS1)
18.5.3.1 Transmit FIFO Service (TFS)
18.5.3.2 Transmit Packet Complete (TPC)
18.5.3.3 Flush Tx FIFO (FTF)
18.5.3.4 Transmit Underrun (TUR)
18.5.3.5 Sent STALL (SST)
18.5.3.6 Force STALL (FST)
18.5.4 UDC Endpoint 2 Control/Status Register (UDCCS2)
18.5.4.1 Receive FIFO Service (RFS)
18.5.4.2 Receive Packet Complete (RPC)
18.5.4.3 Bit 2 Reserved
18.5.4.4 Bit 2 Reserved
18.5.4.5 Sent Stall (SST)
18.5.4.8 Receive Short Packet (RSP)
18.5.5 UDC Endpoint 3 Control/Status Register (UDCCS3)
18.5.5.1 Transmit FIFO Service (TFS)
18.5.5.2 Transmit Packet Complete (TPC)
18.5.5.3 Flush Tx FIFO (FTF)
18.5.5.4 Transmit Underrun (TUR)
18.5.6 UDC Endpoint 4 Control/Status Register (UDCCS4)
18.5.6.1 Receive FIFO Service (RFS)
18.5.6.2 Receive Packet Complete (RPC)
18.5.6.3 Receive Overflow (ROF)
18.5.6.4 Bit 3 Reserved
18.5.6.5 Bit 4 Reserved
18.5.6.6 Bit 5 Reserved
18.5.7 UDC Endpoint 5 Control/Status Register (UDCCS5)
18.5.7.1 Transmit FIFO Service (TFS)
18.5.7.2 Transmit Packet Complete (TPC)
18.5.7.3 Flush Tx FIFO (FTF)
18.5.7.4 Transmit Underrun (TUR)
18.5.7.5 Sent STALL (SST)
18.5.7.6 Force STALL (FST)
18.5.7.7 Bit 6 Reserved
18.5.8 UDC Endpoint 6 Control/Status Register (UDCCS6)
18.5.8.1 Transmit FIFO Service (TFS)
18.5.8.2 Transmit Packet Complete (TPC)
18.5.8.3 Flush Tx FIFO (FTF)
18.5.8.4 Transmit Underrun (TUR)
18.5.8.5 Sent STALL (SST)
18.5.8.7 Bit 6 Reserved
18.5.8.8 Transmit Short Packet (TSP)
18.5.9 UDC Endpoint 7 Control/Status Register (UDCCS7)
18.5.9.1 Receive FIFO Service (RFS)
18.5.9.2 Receive Packet Complete (RPC)
18.5.9.3 Bit 2 Reserved
18.5.9.4 Bit 3 Reserved
18.5.9.7 Receive FIFO Not Empty (RNE)
18.5.9.8 Receive Short Packet (RSP)
18.5.10 UDC Endpoint 8 Control/Status Register (UDCCS8)
18.5.10.1 Transmit FIFO Service (TFS)
18.5.10.2 Transmit Packet Complete (TPC)
18.5.10.3 Flush Tx FIFO (FTF)
18.5.10.4 Transmit Underrun (TUR)
18.5.10.6 Bit 5 Reserved
Bit 5 is reserved for future use.
18.5.10.7 Bit 6 Reserved
18.5.10.8 Transmit Short Packet (TSP)
18.5.11 UDC Endpoint 9 Control/Status Register (UDCCS9)
18.5.11.1 Receive FIFO Service (RFS)
18.5.11.2 Receive Packet Complete (RPC)
18.5.11.3 Receive Overflow (ROF)
18.5.11.4 Bit 3 Reserved
18.5.12 UDC Endpoint 10 Control/Status Register (UDCCS10)
18.5.12.1 Transmit FIFO Service (TFS)
18.5.12.2 Transmit Packet Complete (TPC)
18.5.12.3 Flush Tx FIFO (FTF)
18.5.12.4 Transmit Underrun (TUR)
18.5.12.5 Sent STALL (SST)
18.5.12.6 Force STALL (FST)
18.5.12.7 Bit 6 Reserved
18.5.13 UDC Endpoint 11 Control/Status Register (UDCCS11)
18.5.13.1 Transmit FIFO Service (TFS)
18.5.13.2 Transmit Packet Complete (TPC)
18.5.13.3 Flush Tx FIFO (FTF)
18.5.13.4 Transmit Underrun (TUR)
18.5.13.5 Sent STALL (SST)
18.5.13.7 Bit 6 Reserved
18.5.13.8 Transmit Short Packet (TSP)
18.5.14 UDC Endpoint 12 Control/Status Register (UDCCS12)
18.5.14.1 Receive FIFO Service (RFS)
18.5.14.2 Receive Packet Complete (RPC)
18.5.14.3 Bit 2 Reserved
18.5.14.4 Bit 3 Reserved
18.5.14.6 Force Stall (FST)
18.5.14.7 Receive FIFO Not Empty (RNE)
18.5.14.8 Receive Short Packet (RSP)
18.5.15 UDC Endpoint 13 Control/Status Register (UDCCS13)
18.5.15.1 Transmit FIFO Service (TFS)
18.5.15.2 Transmit Packet Complete (TPC)
18.5.15.3 Flush Tx FIFO (FTF)
18.5.15.4 Transmit Underrun (TUR)
18.5.15.5 Bit 4 Reserved
18.5.15.6 Bit 5 Reserved
18.5.15.7 Bit 6 Reserved
18.5.15.8 Transmit Short Packet (TSP)
18.5.16 UDC Endpoint 14 Control/Status Register (UDCCS14)
18.5.16.1 Receive FIFO Service (RFS)
18.5.16.2 Receive Packet Complete (RPC)
18.5.16.3 Receive Overflow (ROF)
18.5.16.4 Bit 3 Reserved
18.5.16.7 Receive FIFO Not Empty (RNE)
18.5.16.8 Receive Short Packet (RSP)
18.5.17 UDC Endpoint 15 Control/Status Register (UDCCS15)
18.5.17.1 Transmit FIFO Service (TFS)
18.5.17.2 Transmit Packet Complete (TPC)
18.5.17.3 Flush Tx FIFO (FTF)
18.5.17.4 Transmit Underrun (TUR)
18.5.17.5 Sent STALL (SST)
18.5.17.6 Force STALL (FST)
18.5.17.7 Bit 6 Reserved
18.5.17.8 Transmit Short Packet (TSP)
18.5.18 UDC Interrupt Control Register 0 (UICR0)
18.5.18.1 Interrupt Mask Endpoint x (IMx), Where x is 0 through 7
18.5.19 UDC Interrupt Control Register 1 (UICR1)
18.5.19.1 Interrupt Mask Endpoint x (IMx), where x is 8 through 15.
18.5.20 UDC Status/Interrupt Register 0 (UISR0)
18.5.20.1 Endpoint 0 Interrupt Request (IR0)
18.5.20.2 Endpoint 1 Interrupt Request (IR1)
18.5.20.3 Endpoint 2 Interrupt Request (IR2)
18.5.20.4 Endpoint 3 Interrupt Request (IR3)
18.5.20.5 Endpoint 4 Interrupt Request (IR4)
18.5.20.7 Endpoint 6 Interrupt Request (IR6)
18.5.20.8 Endpoint 7 Interrupt Request (IR7)
18.5.21 UDC Status/Interrupt Register 1 (USIR1)
18.5.21.1 Endpoint 8 Interrupt Request (IR8)
18.5.21.2 Endpoint 9 Interrupt Request (IR9)
18.5.21.3 Endpoint 10 Interrupt Request (IR10)
18.5.21.4 Endpoint 11 Interrupt Request (IR11)
18.5.22 UDC Frame Number High Register (UFNHR)
18.5.22.1 UDC Frame Number MSB (FNMSB)
18.5.22.2 Isochronous Packet Error Endpoint 4 (IPE4)
18.5.22.3 Isochronous Packet Error Endpoint 9 (IPE9)
18.5.22.4 Isochronous Packet Error Endpoint 14 (IPE14)
18.5.22.5 Start of Frame Interrupt Mask (SIM)
18.5.22.6 Start of Frame Interrupt Request (SIR)
18.5.23 UDC Frame Number Low Register (UFNLR)
18.5.24 UDC Byte Count Register 2 (UBCR2)
The Byte-Count Register maintains the remaining byte count in the active buffer of OUT endpoint2.
18.5.24.1 Endpoint 2 Byte Count (BC[7:0])
18.5.25 UDC Byte Count Register 4 (UBCR4)
18.5.25.1 Endpoint 4 Byte Count (BC[7:0])
18.5.26 UDC Byte Count Register 7 (UBCR7)
18.5.26.1 Endpoint 7 Byte Count (BC[7:0])
18.5.27 UDC Byte Count Register 9 (UBCR9)
18.5.27.1 Endpoint 9 Byte Count (BC[7:0])
18.5.28 UDC Byte Count Register 12 (UBCR12)
18.5.28.1 Endpoint 12 Byte Count (BC[7:0])
18.5.29 UDC Byte Count Register 14 (UBCR14)
18.5.29.1 Endpoint 14 Byte Count (BC[7:0])
18.5.30 UDC Endpoint 0 Data Register (UDDR0)
18.5.31 UDC Data Register 1 (UDDR1)
18.5.32 UDC Data Register 2 (UDDR2)
18.5.33 UDC Data Register 3 (UDDR3)
18.5.34 UDC Data Register 4 (UDDR4)
18.5.35 UDC Data Register 5 (UDDR5)
18.5.36 UDC Data Register 6 (UDDR6)
18.5.37 UDC Data Register 7 (UDDR7)
18.5.38 UDC Data Register 8 (UDDR8)
18.5.39 UDC Data Register 9 (UDDR9)
18.5.40 UDC Data Register 10 (UDDR10)
18.5.41 UDC Data Register 11 (UDDR11)
18.5.42 UDC Data Register 12 (UDDR12)
18.5.43 UDC Data Register 13 (UDDR13)
18.5.44 UDC Data Register 14 (UDDR14)
18.5.45 UDC Data Register 15 (UDDR15)
19.0 UTOPIA Level-2
Page
19.1 UTOPIA Transmit Module
Page
Page
19.2 UTOPIA Receive Module
Page
19.3 UTOPIA-2 Coprocessor / NPE Coprocessor: Bus Interface
19.4 MPHY Polling Routines
19.5 UTOPIA Level-2 Clocks
Page
20.0 JTAG Interface
20.1 TAP Controller
20.1.1 Test-Logic-Reset State
20.1.2 Run-Test/Idle State
20.1.3 Select-DR-Scan State
20.1.4 Capture-DR State
20.1.5 Shift-DR State
20.1.6 Exit1-DR State
20.1.7 Pause-DR State
20.1.8 Exit2-DR State
20.1.9 Update-DR State
20.1.10 Select-IR-Scan State
20.1.11 Capture-IR State
20.1.12 Shift-IR State
20.1.13 Exit1-IR State
20.1.14 Pause-IR State
20.2 JTAG Instructions
20.3 Data Registers
20.3.1 Boundary Scan Register
20.3.2 Instruction Register
20.3.3 JTAG Device ID Register
21.0 AHB Queue Manager (AQM)
21.1 Overview
21.2 Feature List
21.3 Functional Description
21.4 AHB Interface
21.4.1 Queue Control
21.4.2 Queue Status
21.4.2.1 Status Update
21.4.2.2 Flag Bus
Table 177. Queue Status Flags
21.4.2.3 Status Interrupts
21.5 Register Descriptions
21.5.1 Queue Access Word Registers 0 - 63
21.5.2 Queues 0-31 Status Register 0 - 3
21.5.3 Underflow/Overflow Status Register 0 - 1
21.5.4 Queues 32-63 Nearly Empty Status Register
21.5.5 Queues 32-63 Full Status Register
21.5.6 Interrupt 0 Status Flag Source Select Register 0 3
21.5.7 Queue Interrupt Enable Register 0 1
21.5.8 Queue Interrupt Register 0 1
21.5.9 Queue Configuration Words 0 - 63
