Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
September 2006 DM
Order Number: 252480-006US 237
PCI Controller—Intel® IXP42X product line and IXC1100 control plane processors
Additionally, while the AHB Master Interface is in use by a DMA channel, PCI requests
that appear in the Target Receive FIFO are flagged to allow these received requests to
gain access of the AHB bus.
Access to the PCI Controller Control and Status Registers from the AHB is unrestricted
while the DMA channels are operating. The ability to access the PCI Controller Control
and Status Registers is provided to allow the Intel XScale processor to set up the off-
line DMA Register set while the on-line DMA Register set is operating.
When the current transfer is complete, the DMA complete bit is set in the DMA Control
Register (PCI_DMACTRL) and the channel-enable bit is cleared in the Length Register.
If the channel is enabled in the second DMA Length Register, DMA execution starts
using the second set of DMA Registers. Transfers continue in this fashion until the
channel enable bits in both sets of DMA length registers for each channel are set to
logic 0.
Whenever possible, the DMA channels use eight-word burst accesses for the PCI-to-
AHB and AHB-to-PCI transfers. Eight-word bursts are the maximum sustained length
that the AHB — and the PCI bus — can transfer. Every eight words, the PCI bus will
disconnect and reconnect later.
This implementation allows fairness among all devices on the PCI bus. In the general
case, a transfer will issue a beginning burst transfer from one to eight words to align
the AHB word address of the DMA to an eight-word boundary.
The subsequent transfers will be issued as eight-word bursts until the words remaining
to be transferred are eight words or less. The final transfer will complete the DMA with
a burst of one to eight words.
The example below demonstrates how to use the DMA channels.
1. The goal is to:
• Write a 16-word burst to the PCI Bus with no byte-swapping, using the AHB-to-PCI
DMA channel
• Initialize a 16-word burst read from the PCI Bus, using the PCI-to-AHB DMA
channel
• Initialize a six-word burst write to the PCI Bus using the AHB to PCI DMA channel.
The AHB-to-PCI DMA channel is used to complete PCI Memory Cycle write accesses
and the PCI-to-AHB DMA channel is used to complete PCI Memory Cycle read
accesses always.
2. Update the AHB to PCI DMA AHB Address Register 0 (PCI_ATPDMA0_AHBADDR)
with PCI_ATPDMA0_AHBADDR = 0x00004000 and the AHB to PCI DMA PCI Address
Register 0 (PCI_ATPDMA0_PCIADDR) with PCI_ATPDMA0_PCIADDR =
0xFC000004.
3. Update the AHB to PCI DMA AHB Address Register 1 (PCI_ATPDMA1_AHBADDR)
with PCI_ATPDMA1_AHBADDR = 0x00004F00 and the AHB to PCI DMA PCI Address
Register 1 (PCI_ATPDMA1_PCIADDR) with PCI_ATPDMA1_PCIADDR =
0xA2000004.
4. Update the PCI to AHB DMA AHB Address Register 0 (PCI_PTADMA0_AHBADDR)
with PCI_PTADMA0_AHBADDR = 0x00004A00 and the PCI to AHB DMA PCI Address
Register 0 (PCI_PTADMA0_PCIADDR) with PCI_PTADMA0_PCIADDR =
0x10000004.
5. Update the AHB to PCI DMA Length Register 0 (PCI_ATPDMA0_LENGTH) with
PCI_ATPDMA0_LENGTH = 0x80000010.
The DMA write transfer to the PCI bus begins.
6. Update the PCI to AHB DMA Length Register 0 (PCI_PTADMA0_LENGTH) with
PCI_PTADMA0_LENGTH = 0x80000010.