Intel IXC1100, IXP42X 12.3 Using GPIO 14 and GPIO 15 as Clocks

Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
September 2006 DM
Order Number: 252480-006US 389
General Purpose Input/Output (GPIO)—Intel® IXP42X product line and IXC1100 control plane
processors
Once an appropriate interrupt condition is reached, the corresponding bits are set in
the General-Purpose Interrupt Status Register (GPISR). The General-Purpose Interrupt
Status Register can be read in a polled mode or programmed to generate an interrupt.
If a bit is set in the General-Purpose Interrupt Status Register is set, writing logic 1 to
the corresponding set bit in the General-Purpose Interrupt Status Register can clear the
bit. For instance, a value of hexadecimal 0x00002001 is read from the General-Purpose
Interrupt Status Register. The value that is read from the General-Purpose Interrupt
Status Register specifies that GPIO 0 and GPIO 13 both have detected interrupts.
The interrupts can be cleared one-by-one by writing a value hexadecimal value of
0x00002000 to the General-Purpose Interrupt Status Register, followed by writing
hexadecimal 0x00000001. Both interrupts may be cleared simultaneously by writing a
hexadecimal value of 0x00002001 to the General-Purpose Interrupt Status Register.
The General-Purpose Interrupt Status Register will be set to a hexadecimal value of
0x00000000 after receiving a reset. The General-Purpose Interrupt Type Registers will
be set to a hexadecimal value of 0x00000000 after receiving a reset.
It is important to note that level interrupts can only be cleared when the interrupt
condition that caused the interrupt disappears (i.e., input signal level has changed)
whereas edge interrupts can be cleared anytime after the interrupt has occurred.
12.3 Using GPIO 14 and GPIO 15 as Clocks
The GPIO also provides the capability to output two programmable clocks on GPIO14
and GPIO15. The frequency of these two clocks can be up to 33.33 MHz. Writing the
General-Purpose Clock Control Register (GPCLKR) can configure these clocks. The
General-Purpose Clock Control Register is broken up into two major sections, bits 24
through bit 16 for GPIO 15 and bits 8 through bit 0 for GPIO 14. The nine bits of each
section are broken down into three registers, the output control multiplexer register
(MUX15 and MUX14), the clock Frequency Terminal Count Register (CLK1TC and
CLK0TC), and the duty cycle terminal count (CLK1DC and CLK0DC).
The output control multiplexer register is a single-bit register within the General-
Purpose Clock Control Register that determines the location that drives the GPIO. The
two places that the GPIO 14 and GPIO 15 can be driven are the General-Purpose Data
Output Register or the general-purpose clock. When the General-Purpose Output
Enable Register configures GPIO 14 and GPIO15 as outputs, the output control
multiplexer register for GPIO 14 and GPIO 15 are used to determine which location the
GPIO is driven from. When the output control multiplexer is set as logic 0, the GPIO will
be driven from the General-Purpose Data Output Register. When the output control
multiplexer is set as logic 1, the GPIO will be driven from the general-purpose clocks.
The general-purpose clock frequency and duty cycle are programmed by configuring
the clock Frequency Terminal Count Register and the duty cycle terminal count register
which are part of the General-Purpose Clock Control Register. The Frequency Terminal
Count Register and the Duty Cycle Terminal Count Register exist and are separate for
both GPIO 14 and GPIO 15.
Programming a value into the Frequency Terminal Count Register sets the clock period.
The valid frequency values are shown in Tabl e 146.