Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
September 2006 DM
Order Number: 252480-006US 419
Ethernet MAC A—Intel® IXP42X product line and IXC1100 control plane processors
• Bits (25:21) of the MDIO Command (MDIOCMD) Register are used to select the
physical interface that is to accept the transmitted data or return the requested
data.
• Bits (20:16) of the MDIO Command (MDIOCMD) Register are used to select the
register within the physical interface that is to accept the transmitted data or return
the requested data.
• Bit 26 of the MDIO Command (MDIOCMD) Register is used to determine if the
requested command is a read or a write.
— Writing logic 1 to bit 26 of the MDIO Command (MDIOCMD) Register will cause
the transaction to be a write.
— Writing logic 0 to bit 26 of the MDIO Command (MDIOCMD) Register will cause
the transaction to be a read.
Setting Bit 31 of the MDIO Command (MDIOCMD) Register to logic 1 will initiate the
transfer. Bit 31 of the MDIO Command (MDIOCMD) will remain at logic 1 until the
transaction is complete.
Figure 82 shows an example of the data being written from the MII Management
Master (IXP42X product line and IXC1100 control plane processors) to a physical
interface (PHY) using the MDIO interface.
As stated previously, when bit 26 of the MDIO Command (MDIOCMD) Register is set to
logic 0 the Intel XScale processor is requesting a read from a physical interface device
using the MDIO interface. The data that the physical interface returns from the MDIO
signal will be captured in the MDIO STATUS (MDIOSTS) Register.
The MDIO Status Register is broken into four 8-bit registers. The data returned from
the physical interface will be captured in MDIO Status 0 (MDIOSTS0) Register and
MDIO Status 1 (MDIOSTS1) Register:
• MDIO Status 0 (MDIOSTS0) Register corresponds to bits (7:0) of the MDIO Status
(MDIOSTS) Register.
• MDIO Status 1 (MDIOSTS1) Register corresponds to bits (15:8) of the MDIO Status
(MDIOSTS) Register.
• Bits (30:16) of the MDIO Status (MDIOSTS) Register are reserved and will return
zeros when read.
• Bit 31 of the MDIO Status (MDIOSTS) Register will indicate the condition of the
read.
— If logic 1 is read from bit 31 of the MDIO Status (MDIOSTS) Register after a
read transaction from the physical interface is complete, the read contained an
error and should be disregarded.
— If logic 0 is read from bit 31 of the MDIO Status (MDIOSTS) Register after a
read transaction from the physical interface is complete, the read was valid and
error free.
Figure 83 shows an example of the data being read from the physical interface (PHY)
by the MII Management Master (IXP42X product line and IXC1100 control plane
processors) using the MDIO interface. Manipulation of these registers directly may
result in unpredictable behavior. These registers should be manipulated using Intel-
supplied APIs.