Intel IXC1100, IXP42X - page 20

Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor—
Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
DM September 2006
20 Order Number: 252480-006US
38 TX RX Control Register (TXRXCTRL)............................................................................98
39 Normal RX Handshaking............................................................................................99
40 High-Speed Download Handshaking States..................................................................99
41 TX Handshaking.....................................................................................................100
42 TXRXCTRL Mnemonic Extensions..............................................................................101
43 TX Register........................................................................................... .................101
44 RX Register .......................................................................................... .. ...............102
45 DEBUG Data Register Reset Values...........................................................................109
46 CP 14 Trace Buffer Register Summary.......................................................................110
47 Checkpoint Register (CHKPTx)..................................................................................110
48 TBREG Format .................................................................................. .. .. .................111
49 Message Byte Formats............................................................................................112
50 LDIC Cache Functions.............................................................................................118
51 Debug-Handler Code to Implement Synchronization During Dynamic Code Download...... 125
52 Debug Handler Code: Download Bit and Overflow Flag.................................................131
53 Performance Monitoring Registers.............................................................................133
54 Clock Count Register (CCNT)....................................................................................134
55 Performance Monitor Count Register (PMN0 - PMN3)...................................................135
56 Performance Monitor Control Register .......................................................................135
57 Interrupt Enable Register ........................................................................................136
58 Overflow Flag Status Register ..................................................................................137
59 Event Select Register..............................................................................................138
60 Performance Monitoring Events................................................................................139
61 Common Uses of the PMU........................................................................................139
62 Multiply with Internal Accumulate Format..................................................................147
63 MIA{<cond>} acc0, Rm, Rs.....................................................................................147
64 MIAPH{<cond>} acc0, Rm, Rs.................................................................................148
65 MIAxy{<cond>} acc0, Rm, Rs.................................................................................148
66 Internal Accumulator Access Format .........................................................................150
67 MAR{<cond>} acc0, RdLo, RdHi ..............................................................................151
68 MRA{<cond>} RdLo, RdHi, acc0 ..............................................................................151
70 Second-Level Descriptors for Coarse Page Table.........................................................153
71 Second-Level Descriptors for Fine Page Table.............................................................153
69 First-Level Descriptors ............................................................................................153
72 Exception Summary................................................................................................154
73 Event Priority.........................................................................................................155
74 Processors’ Encoding of Fault Status for Prefetch Aborts ..............................................156
75 Intel XScale® Processor Encoding of Fault Status for Data Aborts..................................156
76 Branch Latency Penalty...........................................................................................160
77 Latency Example....................................................................................................162
78 Branch Instruction Timings (Those Predicted by the BTB).............................................162
79 Branch Instruction Timings (Those not Predicted by the BTB).......................................162
80 Data Processing Instruction Timings..........................................................................162
81 Multiply Instruction Timings.....................................................................................163
82 Multiply Implicit Accumulate Instruction Timings.........................................................165
83 Implicit Accumulator Access Instruction Timings.........................................................165
84 Saturated Data Processing Instruction Timings...........................................................165
85 Status Register Access Instruction Timings ................................................................165
86 Load and Store Instruction Timings...........................................................................165
87 Load and Store Multiple Instruction Timings...............................................................166
88 Semaphore Instruction Timings................................................................................166
89 CP15 Register Access Instruction Timings..................................................................166
90 CP14 Register Access Instruction Timings..................................................................166
91 Exception-Generating Instruction Timings..................................................................167
92 Count Leading Zeros Instruction Timings...................................................................167