Intel IXC1100, IXP42X 18.5.10 UDC Endpoint 8 Control/Status Register (UDCCS8)

Intel® IXP42X product line and IXC1100 control plane processors—Universal Serial Bus (USB)
v1.1 Device Controller
Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
DM September 2006
500 Order Number: 252480-006US
18.5.10 UDC Endpoint 8 Control/Status Register (UDCCS8)
The UDC Endpoint 8 Control Status Register contains four bits that are used to operate
endpoint 8, an isochronous IN endpoint.
18.5.10.1 Transmit FIFO Service (TFS)
The transmit FIFO service bit is be set if one or fewer data packets remain in the
transmit FIFO. UDCCS8[TFS] is cleared when two complete data packets are in the
FIFO. A complete packet of data is signified by loading 256 bytes or by setting
UDCCS8[TSP].
18.5.10.2 Transmit Packet Complete (TPC)
The the UDC sets transmit packet complete bit when an entire packet is sent to the
host. When this bit is set, the IR8 bit in the appropriate UDC status/interrupt register is
set if transmit interrupts are enabled.
This bit can be used to validate the other status/error bits in the Endpoint 8 Control/
Status Register. The UDCCS8[TPC] bit gets cleared by writing a 1 to it. This clears the
interrupt source for the IR8 bit in the appropriate UDC status/interrupt register, but the
IR8 bit must also be cleared.
Setting this bit does not prevent the UDC from transmitting the next buffer. The UDC
issues NAK handshakes to all IN tokens if this bit is set and neither buffer has been
triggered by writing 64 bytes or setting UDCCS8[TSP].
18.5.10.3 Flush Tx FIFO (FTF)
The Flush Tx FIFO bit triggers a reset for the endpoint's transmit FIFO. The Flush Tx
FIFO bit is set when software writes a 1 to it or when the host performs a
SET_CONFIGURATION or SET_INTERFACE.
The bit’s read value is 0.
18.5.10.4 Transmit Underrun (TUR)
The transmit underrun bit is be set if the transmit FIFO experiences an underrun. When
the UDC experiences an underrun, UDCCS8[TUR] generates an interrupt.
UDCCS8[TUR] is cleared by writing a 1 to it.
18.5.10.5 Bit 4 Reserved
Bit 4 is reserved for future use.
2 (Reserved). Always reads zero.
1RPC
Receive packet complete (read/write 1 to clear).
0 = Error/status bits invalid.
1 = Receive packet has been received and error/status bits are valid.
0RFS
Receive FIFO service (read-only).
0 = Receive FIFO has less than 1 data packet.
1 = Receive FIFO has 1 or more data packets.
Register UDCCS7 (Sheet 2 of 2)
Bits Name Description