Intel IXC1100, IXP42X 20.1.6 Exit1-DR State, 20.1.7 Pause-DR State, 20.1.8 Exit2-DR State, 20.1.9 Update-DR State

Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
September 2006 DM
Order Number: 252480-006US 551
JTAG Interface—Intel® IXP42X product line and IXC1100 control plane processors
20.1.6 Exit1-DR State
The Exit1-DR state is a temporary controller state. When the TAP controller is in the
Exit1-DR state and JTG_TMS is logic 1 on the rising edge of JTG_TCK, the controller
enters the Update-DR state, which terminates the scanning process. If JTG_TMS is
logic 0 on the rising edge of JTG_TCK, the controller enters the Pause-DR state.
The instruction does not change while the TAP controller is in this state. All test data
registers selected by the current instruction retain their previous value during this
state.
20.1.7 Pause-DR State
The Pause-DR state allows the test controller to temporarily halt the shifting of data
through the test data register in the serial path between JTG_TDI and JTG_TDO. The
test data register selected by the current instruction retains its previous value during
this state. The instruction does not change in this state.
The controller remains in this state as long as JTG_TMS is logic 0. When JTG_TMS
changes to logic 1 on the rising edge of JTG_TCK, the controller moves to the Exit2-DR
state.
20.1.8 Exit2-DR State
The Exit2-DR state is a temporary state. If JTG_TMS is logic 1 on the rising edge of
JTG_TCK, the controller enters the Update-DR state, which terminates the scanning
process. If JTG_TMS is logic 0 on the rising edge of JTG_TCK, the controller enters the
Shift- DR state.
The instruction does not change while the TAP controller is in this state. All test-data
registers selected by the current instruction retain their previous value during this
state.
20.1.9 Update-DR State
The Boundary-Scan Register is provided with a latched, parallel output. This output
prevents changes at the parallel output while data is shifted in response to the
BS_EXTEST and BS_SAMPLE/PRELOAD instructions.
When the Boundary-Scan Register is selected, while the TAP controller is in the Update-
DR state, data is latched onto the Boundary-Scan Register’s parallel output from the
shift-register path on the falling edge of JTG_TCK. The data held at the latched, parallel
output does not change unless the controller is in this state.
Any other test-data register with parallel output registers will be updated with the value
contained in the shift register — for the currently selected test and data register —
when the Update-DR state is entered.
While the TAP controller is in this state, all of the test data register’s shift-register bit
positions selected by the current instruction retain their previous values.
The instruction does not change while the TAP controller is in this state.
When the TAP controller is in the Update-DR state and JTG_TMS is logic 1 on the rising
edge of JTG_TCK, the controller enters the Select-DR-Scan state. If JTG_TMS is logic 0
on the rising edge of JTG_TCK, the controller enters the Run-Test/Idle state.