Intel IXC1100, IXP42X 20.2 JTAG Instructions

Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
September 2006 DM
Order Number: 252480-006US 553
JTAG Interface—Intel® IXP42X product line and IXC1100 control plane processors
The instruction does not change and the instruction register retains its state.
The controller remains in this state as long as JTG_TMS is logic 0. When JTG_TMS
changes to logic 1 on the rising edges of JTG_TCK, the controller moves to the Exit2-IR
state.
20.1.15 Exit2-IR State
The Exit2-IR state is a temporary state. If JTG_TMS is held high on the rising edge of
JTG_TCK, the controller enters the Update-IR state, which terminates the scanning
process. If JTG_TMS is held low on the rising edge of JTG_TCK, the controller enters the
Shift- IR state.
This test data register selected by the current instruction retains its previous value
during this state. The instruction does not change and the instruction register retains
its state.
20.1.16 Update-IR State
The instruction shifted into the instruction register during the Shift-IR state is latched
onto the parallel output from the shift-register path on the falling edge of JTG_TCK.
Once latched, the new instruction becomes the current instruction. Test data registers
selected by the current instruction retain their previous values.
If JTG_TMS is logic 1 on the rising edge of JTG_TCK, the controller enters the Select-
DR-Scan state. If JTG_TMS is logic 0 on the rising edge of JTG_TCK, the controller
enters the Run-Test/Idle state.
20.2 JTAG Instructions
Table174 defines the instructions that either the Intel XScale processor or the IXP42X
product line and IXC1100 control plane processors will implement.
Table 174. JTAG Instruction Set (Sheet 1 of 2)
Op Code
Intel XScale®
Processor or
IXP425 Op Code
(X= XScale,
I = IXP425,
R = Reserved)
Instruction Name Description
0000000 I BS_EXTEST
Extest initiates testing of external circuitry, typically board-level
interconnects and off-chip circuitry. Extest connects the Boundary
Scan register between TDI and TDO in the Shift-DR state. When
Extest is selected, all output signal pin values are driven by values
shifted into the Boundary Scan Register and may change only on the
falling edge of TCK in the Update-DR state. Also, when Extest is
selected the input pin states must be loaded into the Boundary Scan
Register on the rising edge of TCK in the Capture-DR state. Values
shifted into input latches in the Boundary Scan Register are never
used by the processors internal logic for the extest instruction.
0000001 I BS_SAMPLE/PRELOAD
When the TAP controller is in the capture_dr state, the BS_Sample
instruction provides a snapshot of data flowing from the system pins
to the on-chip system logic, or vice versa (without interfering with
normal operation). The snapshot is taken on the rising edge of TCK.
When the TAP controller is in the Update_DR state, the BS_SAMPLE
instruction causes the transfer of data held in the Boundary Scan
cells to the latched, parallel output register cells. Typically, the
latched output data is then applied to the system outputs by means
of the BS_EXTEST instruction.
0000010 X DBGRX Used for accessing the RX Debug Register within the Intel XScale
processor.