Intel® IXP42X product line and IXC1100 control plane processors—Expansion Bus Controller
Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
DM September 2006
294 Order Number: 252480-006US
When bit 31 of the Configuration Register 0 (EXP_CNFG0) is set to logic 1, the
Expansion Bus accesses occupy the lowest 256-Mbytes of address space. When bit 31
of the Configuration Register 0 (EXP_CNFG0) is set to logic 0, the SDRAM occupies the
lowest 256 Mbytes of address.
On reset, bit 31 of the Configuration Register 0 (EXP_CNFG0) is set to logic 1. This
setting is required to allow the boot memory to be accessed which is located at
hexadecimal address 0x00000000 in non-volatile storage on the Expansion Bus.
The first instruction execution of the Intel XScale® Processor is located at address
0x00000000. Once the boot sequence starts, the Intel XScale processor will switch bit
31 of the Configuration Register 0 (EXP_CNFG0) from logic 1 to logic 0, at an
appropriate time.
The information transfer from the flash to the SDRAM can be completed in one of two
ways:
• The configuration bit can be swapped to allow the SDRAM to have access at
address 0x00000000 and the remainder of the flash information can be retrieved
from the expansion-bus address location 0x50000000 to 0x5FFFFFFF
• The SDRAM can be written by writing to the aliased sections of the SDRAM address
space.
The SDRAM only supports a maximum of 256 Mbytes of addressable memory space.
The remaining three memory locations (0x10000000 to 0x1FFFFFFF, 0x20000000 to
0x2FFFFFFF, 0x30000000 to 0x3FFFFFFF) — in the 1-Gbyte address space defined by
the IXP42X product line and IXC1100 control plane processors’ Memory Map — are re-
mapped to the address space located at 0x00000000 to 0x0FFFFFFF.
8.2 Chip Select Address Allocation
The Expansion Bus Controller occupies 256 Mbytes of address space in the IXP42X
product line and IXC1100 control plane processors memory map. The Expansion Bus
Controller uses bits 27:0, from the South AHB, to determine how to translate the South
AHB address to the Expansion Bus Address. The lower 24 bits of the South AHB address
are translated to the lower 24 bits of the Expansion Bus address, EX_ADDR [23:0].
Bits 26:24 of the South AHB are used to decode one of eight chip-select regions
implemented by the expansion bus, each region being 16 Mbytes. Address bit 27 is not
used and will currently alias each chip select region as shown on the left side of
Figure 58.