Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
September 2006 DM
Order Number: 252480-006US 557
AHB Queue Manager (AQM)—Intel® IXP42X product line and IXC1100 control plane processors
Provides Underflow and Overflow Status Flags for each of the queues 0-31
Two Intel XScale processor interrupts, one for queues 0-31 and one for queues 32-
63
Individual interrupt enables for each queue
Programmable interrupt source for each of the queues 0-31 as the assertion or de-
assertion of 1 of 4 status flags, E, NE, NF or F
NE status flag used as the interrupt source for each of the queues 32-63
Provides read/write access to all queues, queue pointers, status flags, configuration
registers, interrupt registers and SRAM via the AHB
21.3 Functional Description
A block diagram of the AHB Queue Manager is shown in Figure 101. The AQM provides
64 independent queues. It maintains these queues as circular buffers in an internal 8KB
SRAM. Status flags are implemented for each queue to indicate relative fullness of each
queue. The status flags for queues 0-31 are mapped and transmitted to the NPEs via
the Flag Bus. External agents, specific to each of the cores, latch queue information
relevant to them from the Flag Bus. Two interrupts, one for queues 0-31 and one for
queues 32-63, are used as queue status interrupts. The AHB interface provides for
complete queue configuration, queue access, queue status access, interrupt
configuration and SRAM access.
The AQM provides for autonomous access to the queues. Via the AHB interface, any
master on the AHB can request a queue read or a queue write operation. The AQM has
no knowledge of either the contents of a queue entry or to whom these queues are
assigned, or what are the contents or semantic meaning of the queue. The AQM will
respond to a queue request by fetching the read or write pointer to the requested
queue and then perform the requested operation. For a queue read request, the data is
Figure 101. AHB Queue Manager
NPEs
XScale
AHB
FLAG BUS
AHB QUEUE MANAGER
Queue
Buffer
SRAM
Queue
Control AHB
Slave
Config/Status
Registers INT
MUX BUS