Intel IXC1100, IXP42X - page 65

Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
September 2006 DM
Order Number: 252480-006US 65
Intel XScale® Processor—Intel® IXP42X product line and IXC1100 control plane processors
The data cache and mini-data cache are protected by parity to ensure data integrity;
there is one parity bit per byte of data. (The tags are NOT parity protected.) When a
parity error is detected on a data/mini-data cache access, a data abort exception
occurs. Before servicing the exception, hardware will set bit 10 of the Fault Status
Register register.
A data/mini-data cache parity error is an imprecise data abort, meaning R14_ABORT
(+8) may not point to the instruction that caused the parity error. If the parity error
occurred during a load, the targeted register may be updated with incorrect data.
A data abort due to a data/mini-data cache parity error may not be recoverable if the
data address that caused the abort occurred on a line in the cache that has a write-
back caching policy. Prior updates to this line may be lost; in this case the software
exception handler should perform a “clean and clear” operation on the data cache,
ignoring subsequent parity errors, and restart the offending process.
The SWP and SWPB instructions generate an atomic load and store operation allowing
a memory semaphore to be loaded and altered without interruption. These accesses
may hit or miss the data/mini-data cache depending on configuration of the cache,
configuration of the MMU, and the page attributes.
After processor reset, both the data cache and mini-data cache are disabled, all valid
bits are set to zero (invalid), and the round-robin bit points to way 31. Any lines in the
data cache that were configured as data RAM before reset are changed back to
cacheable lines after reset, i.e., there are 32 Kbytes of data cache and zero bytes of
data RAM.
The data cache and mini-data cache are enabled by setting bit 2 in coprocessor 15,
register 1 (Control Register). See “Configuration” on page 73, for a description of this
register and others.
Equation 8 shows code that enables the data and mini-data caches. Note that the MMU
must be enabled to use the data cache.
Individual entries can be invalidated and cleaned in the data cache and mini-data cache
via coprocessor 15, register 7. Note that a line locked into the data cache remains
locked even after it has been subjected to an invalidate-entry operation. This will leave
an unusable line in the cache until a global unlock has occurred. For this reason, do not
use these commands on locked lines.
This same register also provides the command to invalidate the entire data cache and
mini-data cache. Refer to Table18, “Cache Functions” on page 81 for a listing of the
commands. These global invalidate commands have no effect on lines locked in the
data cache. Locked lines must be unlocked before they can be invalidated. This is
accomplished by the Unlock Data Cache command found in Tabl e 20 , “C ach e L ock-
Down Functions” on page 83.
Example 8. Enabling the Data Cache
enableDCache:
MCR p15, 0, r0, c7, c10, 4; Drain pending data operations...
; (see Chapter 7.2.8, Register 7: Cache functions)
MRC p15, 0, r0, c1, c0, 0; Get current control register
ORR r0, r0, #4 ; Enable DCache by setting ‘C’ (bit 2)
MCR p15, 0, r0, c1, c0, 0; And update the Control register