Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
September 2006 DM
Order Number: 252480-006US 21
—Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
93 Pipelines and Pipe Stages........................................................................................169
94 Network Processor Functions................................................................................... 202
95 Bus Arbitration Example: Three Requesting Masters ...................................................205
96 Memory Map.........................................................................................................206
97 PCI Target Interface Supported Commands............................................................... 211
98 PCI Initiator Interface-Supported Commands.............................................................212
99 PCI Memory Map Allocation..................................................................................... 221
100 PCI Byte Enables Using CRP Access Method ...............................................................224
101 PCI Configuration Space..........................................................................................225
102 Command Type for PCI Controller Configuration and Status Register Accesses ............... 225
103 PCI Configuration Register Map................................................................................ 249
104 PCI Controller CSR Address Map...............................................................................258
105 Supported Configuration of the SDRAM Controller.......................................................278
106 Memory Space.......................................................................................................279
107 Memory Configurations for Writing the SDRAM Configuration (SDR_CONFIG) Register ..... 280
108 Memory Configurations for Writing the SDRAM Configuration (SDR_CONFIG) Register ..... 280
109 SDRAM Command Description .................................................................................281
110 SDRAM I/O For Various Commands ..........................................................................282
111 Page Register Allocation..........................................................................................284
112 Data Transfer Sizes of AHB......................................................................................285
113 SDRAM Register Overview.......................................................................................287
114 SDRAM Configuration Options.................................................................................. 289
115 SDRAM Burst Definitions ......................................................................................... 289
116 SDRAM Commands.................................................................................................290
117 Processors’ Trimmed Version of the Memory Map .......................................................293
118 Expansion Bus Address and Data Byte Steering.......................................................... 296
119 Expansion Bus Cycle Type Selection .........................................................................298
120 Multiplexed Output Pins for HPI Operation ................................................................. 303
121 HPI HCNTL Control Signal Decoding.......................................................................... 304
122 Expansion Bus Register Overview............................................................................. 319
123 Bit Level Definition for each of the Timing and Control Registers................................... 322
124 Configuration Register 0 Description .........................................................................323
125 Intel XScale® Processor Speed Expansion Bus Configuration Strappings ........................324
126 Expansion Bus Configuration Register 1-Bit Definition .................................................325
127 Simulated Expansion Bus Performance......................................................................326
128 Address Map for the APB.........................................................................................330
129 Typical Baud Rate Settings...................................................................................... 335
130 UART Transmit Parity Operation............................................................................... 337
131 UART Receive Parity Operation ................................................................................337
132 UART Word-Length Select Configuration....................................................................338
133 UART FIFO Trigger Level .........................................................................................343
134 High-Speed UART Registers Overview....................................................................... 344
135 UART IDD Bit Mapping............................................................................................349
136 Console UART Registers Overview ............................................................................357
137 Priority Levels of Interrupt Identification Register .......................................................361
138 UART Interrupt Identification Bit Level Definition ........................................................362
139 Bus Arbitration Example: Three Requesting Masters ................................................... 373
140 Memory Map .........................................................................................................374
141 GPIO Interrupt Selections .......................................................................................378
142 GPIO Clock Frequency Select................................................................................... 380
143 GPIO Duty Cycle Select...........................................................................................380
144 GPIO Registers Overview ........................................................................................381
145 Interrupt Controller Registers ..................................................................................391
146 Timer Registers .....................................................................................................401
147 Processors’ Devices with Ethernet Interface ...............................................................406