Intel IXC1100, IXP42X 15.2.6 Threshold For Partially Empty, 15.2.7 Threshold For Partially Full, 15.2.8 Buffer Size For Transmit

Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
September 2006 DM
Order Number: 252480-006US 431
Ethernet MAC A—Intel® IXP42X product line and IXC1100 control plane processors
15.2.6 Threshold For Partially Empty
15.2.7 Threshold For Partially Full
15.2.8 Buffer Size For Transmit
Register Name: threshpe
Hex Offset Address: 0xC8009030 Reset Hex Value: 0x00000000
Register
Description: FIFO Partially Full/Empty Threshold Register. The threshold is the number of 32-bit words in the FIFO.
Access: Read/Write.
31 87 0
(Reserved) Partial Empty
Register threshpe
Bits Name Description
31:8 (Reserved)
7:0 Partial Empty
Marks the partial empty thresholds of the Transmit FIFO and Receive FIFO.
When the number of entries in the Transmit FIFO is less than or equal to the
contents of this register, tx_fifo_p_empty is asserted. When the number of
entries in the Receive FIFO is less than or equal to the contents of this register,
rx_fifo_p_empty is asserted.
Register Name: threshpf
Hex Offset Address: 0xC8009038 Reset Hex Value: 0x00000000
Register
Description: FIFO Partially Full/Empty Threshold Register. The threshold is the number of 32-bit words in the FIFO.
Access: Read/Write.
31 87 0
(Reserved) Partial Full
Register threshpf
Bits Name Description
31:8 (Reserved)
7:0 Partial Full
Marks the partial full thresholds of the Transmit FIFO and Receive FIFO. When
the number of entries in the Transmit FIFO is greater than or equal to the
contents of this register, tx_fifo_p_full is asserted. When the number of entries
in the Receive FIFO is greater than or equal to the contents of this register,
rx_fifo_p_full is asserted.
Register Name: txbuffsize
Hex Offset Address: 0xC8009040 Reset Hex Value: 0x00000000
Register
Description: Transmit Buffer Size Register
Access: Read/Write.
31 87 0
(Reserved) Tx Buffer Size